[SI-LIST] Re: slew rate and driver impedance




The third way is to use a well controlled large driver with an internal
series resistor.  The drawback is the equivalent capacitive loading
might be too large.  There is always a desire to tune the output resistance
and slew rate independently that meeting the I/O spec is easier.

Raymond






"Ingraham, Andrew" <Andrew.Ingraham@xxxxxx> on 26/09/2002 04:48:03

Please respond to Andrew.Ingraham@xxxxxx

To:   si-list@xxxxxxxxxxxxx
cc:    (bcc: Raymond Leung/sdc)

Subject:  [SI-LIST] Re: slew rate and driver impedance



>  Can a driver(FPGA) with
> two different slew rate options have the same
> output impedance ?

Yes.  Drivers can be made with intentionally slowed down slew rates,
without affecting the steady-state output impedance.

I'm not an IC designer, but two possible ways to do this might be (1) by
slowing down the gate drive sufficiently to the output transistors, the
transistors switch more slowly; or (2) use multiple output transistors
with staggered drive signals.

Andy









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