> Can a driver(FPGA) with > two different slew rate options have the same > output impedance ? Yes. Drivers can be made with intentionally slowed down slew rates, without affecting the steady-state output impedance. I'm not an IC designer, but two possible ways to do this might be (1) by slowing down the gate drive sufficiently to the output transistors, the transistors switch more slowly; or (2) use multiple output transistors with staggered drive signals. Andy ------------------------------------------------------------------ To unsubscribe from si-list: si-list-request@xxxxxxxxxxxxx with 'unsubscribe' in the Subject field or to administer your membership from a web page, go to: http://www.freelists.org/webpage/si-list For help: si-list-request@xxxxxxxxxxxxx with 'help' in the Subject field List archives are viewable at: http://www.freelists.org/archives/si-list or at our remote archives: http://groups.yahoo.com/group/si-list/messages Old (prior to June 6, 2001) list archives are viewable at: http://www.qsl.net/wb6tpu