[SI-LIST] Re: si-list Digest V8 #22

You can gain a lot of insight by just using the tools that the capacitor
suppliers provide for free.  KEMET Spice is very useful, and Murata also
has a useful tool, along with many others.  These tools won't provide
the response in your circuit, but you have to start somewhere.  All the
tools also provide simulation models that you can use with SPICE or a RF
simulator.  KEMET Spice provides the most complex models that show many
resonances.  In all the tools, add the capacitors you want to use, then
use the combine command to get the combined response.  The RF simulators
also come with good capacitor models from various suppliers.  The best
example for your talk is to use a common circuit that you all use rather
than a paper that is most likely to show some far-out application that
doesn't apply to you.

I'm replying just to you because replying to all means I have to sort
out autoreplies for the next two days.  I'd rather keep it simple, but
if you find the information useful, forward it to whomever you like.

 

-----Original Message-----
From: FreeLists Mailing List Manager [mailto:ecartis@xxxxxxxxxxxxx] 
Sent: Tuesday, January 22, 2008 1:29 AM
To: si-list digest users
Subject: si-list Digest V8 #22

si-list Digest  Mon, 21 Jan 2008        Volume: 08  Issue: 022

In This Issue:
        #1:     From: "Kivity Kobi" <kobik@xxxxxxxxxxx>
                Subject: [SI-LIST] Capacitor in parallel
        #2:     From: "Jose Schutt-Aine" <jsa@xxxxxxxxxxxxxx>
                Subject: [SI-LIST] SECOND CALL FOR PAPERS: SPI'08
        #3:     From: "Jose Schutt-Aine" <jose@xxxxxxxxxxxxxx>
                Subject: [SI-LIST] SECOND CALL FOR PAPERS: SPI'08
        #4:     From: "Lu, Devis" <Devis.Lu@xxxxxxxxxxxx>
                Subject: [SI-LIST] 0.9 mil,0.8 mil,0.7mil gold wire
application for I
        #5:     From: "Sadakathullah Mohamed Ali (mohamali)"
<mohamali@xxxxxxxxx>
                Subject: [SI-LIST] Cisco Systems - Sr. Signal Integrity
Engineer posi
        #6:     From: "Kyoungchoul Koo" <kckoo1984@xxxxxxxxx>
                Subject: [SI-LIST] The current distribution and partial
self-inductan

----------------------------------------------------------------------

Msg: #1 in digest
Subject: [SI-LIST] Capacitor in parallel
Date: Mon, 21 Jan 2008 17:14:17 +0200
From: "Kivity Kobi" <kobik@xxxxxxxxxxx>

Hi Gurus,

I need to give a lecture on subject that related to signal integrity in
our next group meeting and I choose to talk about how much capacitor we
needs and what happen when we put capacitor in parallel with difference
case and value (100nF parallel with 10uF), what some times we see in
data sheets, and show the resonance between the inductances of the Bulk
capacitors to the bypass capacitors.

I appreciate if you send me links to good article about this subjects or
anything else that=3D20 regards to that subjects

Thanks!
Kobi

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------------------------------

Msg: #2 in digest
From: "Jose Schutt-Aine" <jsa@xxxxxxxxxxxxxx>
Subject: [SI-LIST] SECOND CALL FOR PAPERS: SPI'08
Date: Mon, 21 Jan 2008 11:24:50 -0600

SECOND CALL FOR PAPERS: SPI'08


The 12th IEEE Workshop on Signal Propagation on Interconnects will take
place, first time in France, in Avignon, May 12-15, 2008.

Sponsored by the IEEE Computer Society - Test Technology Technical
Council
(TTTC)
and by the IEEE Components, Packaging, and Manufacturing Technology
(CPMT) Society.


You are strongly encouraged to submit your latest research results as a
paper to the conference. Full information about SPI'08, including
submission details, can be found at :

http://spi.univ-brest.fr

Authors should submit a pdf version of their papers through web-based
submission interface, as described on SPI website.

IMPORTANT DATES ARE;
Paper Submission deadline: February, 8th, 2008.
Acceptance Notification: March, 15th, 2008.


Best regards,
Denis DESCHACHT and F. HURET
General and Co-Chairs.


------------------------------

Msg: #3 in digest
From: "Jose Schutt-Aine" <jose@xxxxxxxxxxxxxx>
Subject: [SI-LIST] SECOND CALL FOR PAPERS: SPI'08
Date: Mon, 21 Jan 2008 10:50:30 -0600


SECOND CALL FOR PAPERS: SPI'08


The 12th IEEE Workshop on Signal Propagation on Interconnects will take
place, first time in France, in Avignon, May 12-15, 2008.

Sponsored by the IEEE Computer Society - Test Technology Technical
Council
(TTTC)
and by the IEEE Components, Packaging, and Manufacturing Technology
(CPMT) Society.


You are strongly encouraged to submit your latest research results as a
paper to the conference. Full information about SPI'08, including
submission details, can be found at :

http://spi.univ-brest.fr

Authors should submit a pdf version of their papers through web-based
submission interface, as described on SPI website.

IMPORTANT DATES ARE;
Paper Submission deadline: February, 8th, 2008.
Acceptance Notification: March, 15th, 2008.


Best regards,
Denis DESCHACHT and F. HURET
General and Co-Chairs.


------------------------------

Msg: #4 in digest
Subject: [SI-LIST] 0.9 mil,0.8 mil,0.7mil gold wire application for IC
packagi
Date: Tue, 22 Jan 2008 09:10:50 +0800
From: "Lu, Devis" <Devis.Lu@xxxxxxxxxxxx>

Dear si-listers:
 As Gold wire price keep increasing in recent year, we are working on
evaluate 0.9mil,0.8mil, and 0.7 mil gold wire for wirebonding MCP
package. But we have some SI concerns if we reduce the gold wire
diameters although our current product speed is only 133MHZ . Does
anyone have study this before,and come out design rule Gold Wire
Diameter Vs max wire length?
Regards
Davis



------------------------------

Msg: #5 in digest
Subject: [SI-LIST] Cisco Systems - Sr. Signal Integrity Engineer
position
Date: Mon, 21 Jan 2008 18:43:39 -0800
From: "Sadakathullah Mohamed Ali (mohamali)" <mohamali@xxxxxxxxx>

Hi Members
 
I am sending this email on behalf of Director of Hardware Engineering at
Cisco in San Jose, CA. He is looking to add a SI engineer to his team.
If interested please email your resume to mohamali@xxxxxxxxx
 
Cisco Systems - San Jose, CA:
 
Sr. Signal Integrity Engineer
We are looking for an experienced Signal Integrity Engineer to join a
team responsible for the architecture, implementation, and verification
of computer-switching systems, using 5Gb/s - 10Gb/s serial links. 

The candidate will participate in system design, signal integrity
analysis, and validation of a variety of multi-gigabit interconnects:
back-plane links, passive copper cabling, active copper cabling and
optic cables. These solutions will provide industry leading
computer-server interconnects at rates ranging from 20Gb/s to 40Gb/s.
The candidate will also have opportunities to participate, and to
contribute to standard bodies.

A BSEE degree with 10+ years or a MSEE with 4+ years of experience in SI
work is required. 

Candidate must have the following skills: 

In depth knowledge of high-speed design, transmission-line theory and
field-solving methods. 
S-Parameter modeling and simulation. 
Proficiency with HSPICE (or equivalent) circuit simulation tools. 
Proficiency with 2D and 3D field-solvers, such as ANSOFT HFSS. 
Proficiency with cross talk analysis. 
Experience correlating simulation results with lab measurements using
oscilloscopes, TDRs, VNAs, and spectrum analyzers. 
Good verbal and written skills (candidate will be expected to document
design requirements, specifications, application notes, white papers,
and various technical collateral).
 
Thanks and Regards
 
Mohamed Ali
mohamali@xxxxxxxxx
510-402-7625


------------------------------

Msg: #6 in digest
Date: Tue, 22 Jan 2008 14:45:58 +0900
From: "Kyoungchoul Koo" <kckoo1984@xxxxxxxxx>
Subject: [SI-LIST] The current distribution and partial self-inductance

Hi all,


I have a question about "partial self inductance".

which is introduced in "Signal integrity : Simplified" by Eric Bogatin.



By the definition of partial self inductance, (partial self inductance
is the # of field line loops around a "conductor" per current)

I thought the partial self inductance has only a relationship with the
amount of current enclosed by the field line loops.



But this book says("Signal integrity : Simplified" by Eric Bogatin
p.160) that the partial self inductance varies with the cross-sectional
area of conductor.

It means if we make the radius of round rod wire larger, the current
will spread out more and the partial self-inductance will decrease.



Does the size of cross-sectional area of conductor(the current
distribution) affects the # of field line loops around a "conductor", if
the amount of current is fixed?



Does this make sense with the definition of partial self inductance?

Or do I misunderstand something?



Thanks in advance



K.C Koo



------------------------------

End of si-list Digest V8 #22
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