[SI-LIST] Re: si-list Digest V6 #4
- From: Daniel Jones <djones@xxxxxxxxxxxxx>
- To: si-list@xxxxxxxxxxxxx
- Date: Fri, 06 Jan 2006 14:39:46 -0800
FreeLists Mailing List Manager wrote:
si-list Digest Thu, 05 Jan 2006 Volume: 06 Issue: 004
>
>Msg: #2 in digest
>Date: Thu, 5 Jan 2006 22:45:14 +0530
>From: Somesh Dhavala <dhavala.somesh@xxxxxxxxx>
>Subject: [SI-LIST] Re: METASTABILITY
>
>Hi Mike,
>Thank you for your Reply.
>
>How to reduce the metastability by connecting two or more flip flops in
>chain when first flip flop latching wrong data?
>
>
>
I haven't seen anyone reply to this, so I will take a shot at it.
Metastability can occur
when the minimum setup/hold time requirement for a latch is violated.
The most
typical case for this is when data is being transferred between two
different time
domains i.e. where the source clock and receive clock are not synchronized.
Metastability due to improper design is an entirely different problem.
Anyway, when transferring data between time domains, there is no real
concept of
right data or wrong data at the first receiving latch; there is only
delay. Take the case
when there is no change in the data, then the latched data is always
correct.
When a transistion in the data occurs, depending upon the setup/hold time,
the latch will store and output the old data or the new data.
Occasionally, the output
will be indeterminate for a period of time and then settle into one of
the two states.
If the data output of the latch is 'wrong,' then the 'true' data is
delayed by one clock
cycle. This can be bad when data is being sent in parallel.
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