# [SI-LIST] Re: si-list Digest V4 #261

• From: andrew.c.byers@xxxxxxxxxxxxxx
• Date: Thu, 15 Jul 2004 10:30:47 -0700
```Some comments on developing via models, I hope they

I would propose that the model for the via would
consist of the following components:

- an inductive element representing the
transmission line section passing over the hole
in the ground plane caused by the antipad (and representing
the return current divergence to either the ground via or
the virtual gnd plane if it is a diff pair via).

- a capacitive element representing the via pad. The only way
this won't be capacitive is if you somehow have a very wide tline
attached to it such that the pad is nearly the same size as the line.
Not likely, but possible...

- a transmission line element representing the via itself. This does
not have to be inductive - if you look at it as a tline then its
impedance will depend on the location of its partner or ground vias.
Obviously you could use C, R, and L elements to approximate a tline model
if the length & frequency parameters allow it.

The trick is then isolating these elements from each other to
correctly model the physical structure. Clever deembedding like some of
the others have suggested will work. For example, you could simulate (HFSS)
two cases where the via length is different, and the difference between the
two
would give you information as to what the via transmission line element
gain some understanding of their effects on the S-parameters. Matching to
an equivalent circuit then give you your C and L values. However, these
two elements are more difficult to separate because they are just about at
the same
location. It's a matter of how you delineate your models here.

One slight problem with the via model though would be if the stackup you are
using passes through different dielectric layers with different dielectric
constants.
Then you've either got to decide on an effective dielectric constant or
split it up.

Keep in mind that by iterating with a field solver, you might be able to
design
a very clean via transition by adjusting line widths and via spacings. You
will
eventually be limited by the design rules of your technology, but at least
you'll know
that you are optimizing the situation and you'll also know if you have to
for more money to get more design flexability.

regards,

Andy Byers

-----Original Message-----
From: si-list-bounce@xxxxxxxxxxxxx [mailto:si-list-bounce@xxxxxxxxxxxxx] On
Sent: Thursday, July 15, 2004 9:58 AM
To: ndip@xxxxxxxxxxxxxxxxx
Cc: gstokes@xxxxxxxxx; si-list@xxxxxxxxxxxxx
Subject: [SI-LIST] Re: si-list Digest V4 #261

Hello Ivan,

De-embedding the transmission line feeding the via is limited to the
edge of the anti-pad region that the transmission line is referenced to.
That could mean an additional 17.5 mil transmission line for 35mil diameter
anti-pad. The inductance value of this transmission line can be significant
compare with the inductance of the via itself.

Regards,
David

At 05:33 PM 7/15/2004 +0200, Ivan Ndip wrote:
>Hi Goeff,
>when I talk of feeding lines, I mean transmission lines (e.g.,
>microstrip, stripline,...)  that link the via to the wave ports in the
>3D model. These lines, of course, represent the actual trace
>configuration found in the package or PCB. However, if we are
>interesting only in obtaining the inductance of the via, then the
>effects of these lines must be removed through de-embedding at the end
>of the field simulation. The extracted S-parameters can then be used to
>obtain the electrical parameters (e.g., inductance, capacitance,...) of
>the via.
>Your modeling technique is not appropriate enough to be used to extract
>the inductance of a via only. This is because if  the transmission lines
>and vias are  simulated together, and the effects of the lines are not
>removed at the end of the field simulation, then the computed inductance
>value, based on the S-parameters extracted from the field simulation, is
>not only for the via, but for the entire arrangement (via and
>transmission lines).
>I would strongly suggest, that you design and measure test structures,
>in order to validate your modeling approach. There are so many IEEE
>publications on via modeling that may be useful to you.
>
><>
>
>Best regards,
>Ivan Ndip
>
>
>Geoff Stokes wrote:
>
> >Hi Ivan
> >
> >I'm sure your approach is useful.  I would only point out that there
could
> >be inaccuracies.  Where the copper surface current changes direction,
e.g.,
> >from horizontal stripline current to the vertical via, the e-m fields in
the
> >dielectric are somewhat complicated, and are directly related to a
similarly
> >complicated surface current.  Therefore, if sections of track and vias
are
> >treated separately, there will be errors which may or may not be
significant
> >according to the application.
> >
> >As to the size of simulations, certain simple cases of combined
striplines
> >and vias can be reasonably contained in software packages such as Ansoft
> >HFSS or CST Microwave Studio running on a PC (say, 3 GHz Pentium, 512M
RAM).
> >This would certainly help to optimise localised structures forming part
of a
> >larger design.
> >
> >Cheers
> >Geoff
> >
> >
> >
> >>-----Original Message-----
> >>From: Ivan Ndip [mailto:ndip@xxxxxxxxxxxxxxxxx]
> >>Sent: 06 July 2004 11:23
> >>To: Geoff Stokes; si-list@xxxxxxxxxxxxx
> >>Subject: [SI-LIST] Re: si-list Digest V4 #261
> >>
> >>
> >>Hi Geoff,
> >>the feeding lines are considered as ideal, so as to capture only the
> >>effects of the via. The goal is to obtain the inductance of a through
> >>via (of course, with its pads) using HFSS, not a complete
> >>characterization of  all traces and  discontinuities in the
> >>package or
> >>PCB using one HFSS model. If all these are to be considered
> >>in one HFSS
> >>model, then the computation time and memory will be so large,
> >>that the
> >>simulation might not even come to an end.
> >>The traces can be characterized separately, and if they are
> >>uniform over
> >>a given length, then 2D field solvers can also be used.
> >>Certainly, the inductance of a signal via depends on the
> >>location of the
> >>current path associated with the via. If the vias are closely
> >>repeated
> >>in a region as you say, then the inductance becomes a function of the
> >>positions of all the nearby vias. This must be considered as well.
> >>
> >>Regards,
> >>Ivan Ndip
> >>
> >>
> >>
> >>Geoff Stokes wrote:
> >>
> >>
> >>
> >>>I think this is helpful but might not be a complete
> >>>
> >>>
> >>discussion.  It seems to
> >>
> >>
> >>>assume that the wave modes on the connecting copper microstrips or
> >>>striplines are well-characterised.  The de-embedding
> >>>
> >>>
> >>normally uses the
> >>
> >>
> >>>simplest wave mode.  This will often not be representative,
> >>>
> >>>
> >>particularly in
> >>
> >>
> >>>a dense board layout situation.  I'm not exactly sure how to
> >>>
> >>>
> >>
> >>
> >>>I have noticed that the current flow around the via is quite
> >>>
> >>>
> >>complicated.
> >>
> >>
> >>>The impedance is quite sensitive to via position.  Ideally,
> >>>
> >>>
> >>rather than a
> >>
> >>
> >>>single via, the vias should be closely repeated in a region.
> >>>
> >>>
> >> In some RF
> >>
> >>
> >>>applications, to get much lower effective inductance on a
> >>>
> >>>
> >>ground connection,
> >>
> >>
> >>>instead of a row of vias, the board is milled with a slot
> >>>
> >>>
> >>before plating.
> >>
> >>
> >>>Again, the positioning of the slot will be critical.
> >>>
> >>>
> >>>
> >>>
> >>>
> >>>>-----Original Message-----
> >>>>From: Ivan Ndip [mailto:ndip@xxxxxxxxxxxxxxxxx]
> >>>>Sent: 01 July 2004 10:18
> >>>>To: kpalusa@xxxxxxxxx; si-list@xxxxxxxxxxxxx
> >>>>Subject: [SI-LIST] Re: si-list Digest V4 #261
> >>>>=20
> >>>>=20
> >>>>Hi,
> >>>>you have to first develop an EM model of the via, together
> >>>>
> >>>>
> >>with the=20
> >>
> >>
> >>>>planes in HFSS. Use feeding lines to connect the via to the=20
> >>>>wave ports.=20
> >>>>Assign materials to the model, define the ports and set up the=20
> >>>>convergence criteria (e.g., maximum delta_S). At the end of
> >>>>
> >>>>
> >>the field=20
> >>
> >>
> >>>>simulation, remove the effects of the feeding lines through=20
> >>>>de-embedding. You can now use the resulting S-parameters to=20
> >>>>extract the=20
> >>>>electrical parameters (e.g., inductance, capacitance,...)
> >>>>
> >>>>
> >>of the via.=20
> >>
> >>
> >>>>One way of doing this is to use a circuit simulator (e.g.,=20
> >>>>Ansoft, ADS,...). Based on the extracted S-parameters,
> >>>>
> >>>>
> >>develop and=20
> >>
> >>
> >>>>equivalent circuit model of the via and through
> >>>>
> >>>>
> >>optimization, these=20
> >>
> >>
> >>>>electrical parameters can then be obtained.
> >>>>=20
> >>>>Best regards,
> >>>>Ivan Ndip
> >>>>=20
> >>>>=20
> >>>>kusuma palusa wrote:
> >>>>=20
> >>>>
> >>>>
> >>>>
> >>>>
> >>>>>Hello,
> >>>>>=20
> >>>>>Can somebody please suggest how to extract inductance of a=20
> >>>>>
> >>>>>
> >>>>>
> >>>>>
> >>>>through via from HFSS
> >>>>
> >>>>
> >>>>
> >>>>
> >>>>>=20
> >>>>>Thanks
> >>>>>
> >>>>>   =09
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