[SI-LIST] Re: si-list Digest V1 #30
- From: "Ken Cantrell" <Ken.Cantrell@xxxxxxxxxxx>
- To: <si-list@xxxxxxxxxxxxx>
- Date: Fri, 22 Jun 2001 07:09:52 -0600
Chris,
I've copied Charles on this since I haven't reviewed Ansoft yet, maybe he
can give you the straight scoop. Ansoft is such a monolith it would seem
that they would have something so generic as a format translator. Keep me
posted on what you find in a one-size-fits-all package since I'm still
looking also.
Ken
-----Original Message-----
From: si-list-bounce@xxxxxxxxxxxxx
[mailto:si-list-bounce@xxxxxxxxxxxxx]On Behalf Of Chris Renneman
Sent: Thursday, June 21, 2001 1:16 PM
To: si-list@xxxxxxxxxxxxx
Subject: [SI-LIST] Re: si-list Digest V1 #30
Hey everybody,
As newcomer to the world of SI itself, I need some opinions on the best SI
simulation software(s) to use for my applications. My design house uses PADS
PowerPCB for all designs: analog, digital, mixed. In the last month since
I've started here, customers need both pre-layout and pre-fab simulations
like: s-parameter/admittance/reactance/phase data for differential pair
microstrip at 1 GHz on FR4; digital requests for anything from 350ps to 20ps
rise times on FR4 to Rogers matl's; another requesting SPICE sims to run.
Having worked at 4 years Micro Substrates Corp, CAD Designing ceramic BGAs
at 0-30GHZ then testing with a Network Analyzer/PicoProbe setup, I've seen
the disconnect between SONNET modeling and actual s-parameter measurements;
many many model-fab-test cycles.
Is there any one SI software that can handle analog/digital/mixed and
s-parameters with import capability of PADS structures for post layout
simulation while including a Spice engine, or do we need to buy an SI
software seperate to get s-parameter capability?
Hyperlynx can do the A/D/mixed (w/ViewAnalog) and imports PADS, but has only
a Spice writer, a BW capability to maybe 2GHz and no s-parameters. XTK has
the Spice engine, good to 18GHZ, imports PADS, can do A/D/mixed, but again
no s-parameters. Cadence Spectra Quest is similar to XTK but again no
s-parameters.
EagleWare is strictly RF up to 40GHz, does s-parameters, can import Gerbers
for usable post-layout simulation from PADS but no Digital/mixed. Others
like Ansoft, Aplac, Microwave Office, Sigerty, all can't import PADS (so
I've been told)for post-layout SI.
Thanks,
Chris Renneman
M&M Specialties
Tempe, AZ
-----Original Message-----
From: FreeLists Mailing List Manager [mailto:listar@xxxxxxxxxxxxx]
Sent: Wednesday, June 20, 2001 7:01 PM
To: si-list digest users
Subject: si-list Digest V1 #30
si-list Digest Wed, 20 Jun 2001 Volume: 01 Issue: 030
In This Issue:
[SI-LIST] Re: Voltage rating of a Ceramic capacitor
[SI-LIST] Re: set si-list digest2
[SI-LIST] Re: Voltage rating of a Ceramic capacitor
[SI-LIST] Re: Voltage rating of a Ceramic capacitor
[SI-LIST] Re: Voltage rating of a Ceramic capacitor
[SI-LIST] Re: Voltage rating of a Ceramic capacitor
[SI-LIST] Re: Crosstalk between different layers
[SI-LIST] Re: IBIS2XTK v. SPI2MOD
[SI-LIST] copper thickness of a ref plane
[SI-LIST] Re: copper thickness of a ref plane
[SI-LIST] Re: Hspice core dump
[SI-LIST] Re: copper thickness of a ref plane
[SI-LIST] Re: Validation of XTK results for clock skews
----------------------------------------------------------------------
From: HaroldLSJ@xxxxxxx
Date: Wed, 20 Jun 2001 01:32:38 EDT
Subject: [SI-LIST] Re: Voltage rating of a Ceramic capacitor
Ravinder,
I must correct the misinformation you have received concerning the voltage
rating of a ceramic capacitor and in particular for an X7R type dielectric.
First, ALL ceramic capacitors are tested to 2.5 times rated voltage so your
6.3V rating has been 100% tested to 15.75 volts. Further, the typical X7R
MLC (multilayer capacitor) will not breakdown until you reach a voltage
above
500V! The typical breakdown voltage I see is in the 500V to 800V range!
Second, the voltage coefficient for X7R caps at ten (10V) volts is less than
a negative 5% change in capacitance value and at five (5V) volts it is less
than a negative 2% change in capacitance so this will not be a problem.
Third, the typical temperature coefficient for X7R for this voltage range
will not change the capacitance value by more than a negative fifteen (15%)
percent from -55C to +125C and is most likely to be less than -10%.
Fourth, the biggest factor from a SI standpoint is the change in capacitance
value with frequency. This should be qualified on a part by part basis.
The
typical X7R will drop ten (10%) percent of its value from zero to 1MHz so
get
a good high frequency gain/phase meter and compare your tantalum and the X7R
you plan to use then adjust accordingly. If your frequency is extremely
high, consider using a porcelain microwave cap. An NPO cap has almost zero
capacitance drop across this same frequency span.
Remember an MLC is a miniature thick film hybrid circuit so test and mount
the cap with the plates normal (vertical) to the PCB trace.
Finally, ceramic caps like tantalums usually fail by shorting. If you
require high reliability, then request the lot be HALT (highly accelerated
life testing) qualified which is usually a maximum failure rate of between 5
to 8 caps out of 55 tested from the lot you are interested in buying. For
extreme high reliability (zero failures), have the caps 100% HALT sorted.
HALT testing will always find more failures than Mil testing. X7R will
always have a higher reliability than NPO and don't use Z5U or Y5V. There
is
not enough room here to discuss this further so email me direct if you need
more info on reliability.
Harold L. Snyder, Jr.
Scientist & Consultant
Begin Included Message:
==========================
> Subj: [SI-LIST] Voltage rating of a Ceramic capacitor
> Date: 6/14/2001 5:13:41 PM Central Daylight Time
> From: ajmani@xxxxxxxxxx (Ravinder Ajmani)
> Sender: si-list-bounce@xxxxxxxxxxxxx
> Reply-to: si-list@xxxxxxxxxxxxx
> To: si-list@xxxxxxxxxxxxx
>
>
>
> I have been asked to replace Tantalum bulk capacitor in a design with a
> suitable Ceramic capacitor. The Ceramic capacitor is X5R type, which I
> believe is more stable than Y5V. However, its voltage rating being 6.3V,
I
> am not feeling very comfortable to use it in the 5V application. Can
> anyone advise me about the minimum voltage rating I should have for a bulk
> Ceramic capacitor in a 5V application.
>
> Regards, Ravinder
> PCB Development and Design Department
> IBM Corporation
> Email: ajmani@xxxxxxxxxx
>
***************************************************************************
> Always do right. This will gratify some people and astonish the rest.
> .... Mark Twain
>
>
==========================
End Included Message.
------------------------------
From: "Rich Peyton" <p2rich@xxxxxxxxxxxxx>
Subject: [SI-LIST] Re: set si-list digest2
Date: Wed, 20 Jun 2001 08:03:10 -0400
My Input,
If you want to take all that into context SI has been around before the
80's-- Yes it has-- Before being called SI Engineer it was called
"Electronic Engineer/ Technician".
And believe it or not some companies still use the drill trick for the
twisted pair ( Former employer 1 yr. ago )
Rich
-----Original Message-----
From: si-list-bounce@xxxxxxxxxxxxx
[mailto:si-list-bounce@xxxxxxxxxxxxx]On Behalf Of Adam Klein
Sent: Tuesday, June 19, 2001 6:38 PM
To: si-list@xxxxxxxxxxxxx
Subject: [SI-LIST] set si-list digest2
At 09:00 PM 6/18/01 -0500, you wrote:
>si-list Digest Mon, 18 Jun 2001 Volume: 01 Issue: 027
>
>In This Issue:
> [SI-LIST] Re: SI Position Open READ THIS!!!!
> [SI-LIST] Re: 1GHz clock needed, please share your info
with
> [SI-LIST] measuring Hi-Z and Lo-Z state
> [SI-LIST] Improve the heat on a PCB
> [SI-LIST] Re: Improve the heat on a PCB
> [SI-LIST] Hspice core dump
> [SI-LIST] Re: Hspice core dump
> [SI-LIST] Re: Hspice core dump
> [SI-LIST] Re: Voltage rating of a Ceramic capacitor
> [SI-LIST] FYI: Solder ...
> [SI-LIST] Re: SI Position Open READ THIS!!!!
> [SI-LIST] Re: SI Position Open READ THIS!!!!
> [SI-LIST] Re: SI Position Open READ THIS!!!!
> [SI-LIST] Re: SI Position Open READ THIS!!!!
> [SI-LIST] Re: SI Position Open READ THIS!!!!
> [SI-LIST] Re: SI Position Open READ THIS!!!!
> [SI-LIST] Re: Inductance of Via
> [SI-LIST] Re: SI Position Open READ THIS!!!!
> [SI-LIST] Re: Improve the heat on a PCB
>
>----------------------------------------------------------------------
>
>From: "Greim, Michael" <mgreim@xxxxxxxxxxxx>
>Subject: [SI-LIST] Re: SI Position Open READ THIS!!!!
>Date: Mon, 18 Jun 2001 08:20:43 -0400
>
>
>Hi Bo,
>
>I am not sure if you were aware that high speed ecl based
>systems were being designed well before 94-95 and that even
>the tools such as TLC to solve these problems were available
>before that time as well. I remember solving noise and power
>problems early to mid 80s. You young folks might not remember
>when big systems were prototyped with 3 deep 9u wire wrap
>boards. There was plenty of noise to be had on those.
>
>hey, anybody remember making twisted pair wire wrap wire by
>putting two pieces of wire wrap wire in a drill. Those were
>the days my friend.
>
>Ya know, I have been working on SI and I can tell you that there
>aren't many people who know how long SI has been around. There
>are also a number of folks who believe that frequency is what drives
>the need.
>
>SI not an issue at lower speeds. Yikes! This is probably one of the
>more entertaining SI issues to solve today as newer technologies
>with more agressive edge rates are dropped into legacy boards
>designed when SI was not taken into consideration. While there is
certainly
>a correlation between edge rate and frequency, edge rate is where
>the focus needs to be regardless of frequency.
>
>What I'm trying to say is that your post will make some people
>laugh. (perhaps not quite so much as posting 15 megs of files
>to over 2K people).
>
>
>The above post has been entertainingly posted with the following
>blanket obligatory ;-) 8-). Many of the above lines were stolen
>without permission from the original author of the attached post.
>
>Best Regards,
>
>Michael C. Greim Sonus Networks
>mgreim@xxxxxxxxxxxx 978-589-8336
>
>Making the world safe for digital signals everywhere
>
>And all this science I don't understand
>It's just my job six days a week
>
>The time is gone. The email's over
>Thought I'd something more to say......
>
>
>-----Original Message-----
>From: Bo [mailto:bo_pfc@xxxxxxxxx]
>Sent: Friday, June 15, 2001 9:45 PM
>To: si-list@xxxxxxxxxxxxx
>Subject: [SI-LIST] Re: SI Position Open READ THIS!!!!
>
>
>
>Hi Esther,
>
>I am not sure if you are aware but Signal Integrity did show up until
94-95.
>
>The only person to satisfy your requirements is Howard Johnson aka author
of
>first book on SI "Book of Black Magic". What I am trying to say is that
>your
>post will make some people laugh. Don't worry you are not the first one
>with
>similar post. What you should have wrought is "8 years of high speed PCB
>board
>design with emphasis on signal integrity". That would be more belivable.
>The SI wasn't issue at lower speeds. It has shown up in last few years as
a
>mayor issue. I have been working on SI and I can tell you there aren't
that
>many people who really know SI. You should look for a person who has
>designed
>whole lot of backplanes and who has done SI simulations on their own (not
>someone who got other people to do it for them).
>
>I hope this helps you. And I hope you find right person for the job.
>
>
>Regards,
>Bo
>
>p.s. If you need help being more specific in your search feel free to
>contact
>me.
>p.p.s. I am not looking for a job and I probably wouldn't fit your
>qualifications. I am just trying to help.
>
>--- esther williams <estherw2000@xxxxxxxxx> wrote:
> >
> > Hello - The following is a SI position at an Optical Data Networking
start
> > up.
> >
> > Please contact: Esther at ewilliams@xxxxxxxxxxxx for more information.
> >
> > Title: Senior Signal Integrity Engineer
> >
> > Location: Mountain View, CA
> >
> > Job Description:
> >
> > - Specify, simulate, design and analyze high speed interfaces for data
> > networking systems.
> >
> > - Verification of actual hardware and confirm the simulations results to
> > guarantee integrity of all the high speed interfaces.
> >
> > - Generate guide lines for board designers and layout designers for the
>high
> > speed routing.
> >
> > - Setup process to sign off layouts for PCB fabs.
> >
> > Position Requirements:
> >
> > - Experience with high speed IOs like LVDS, HSTL, SSTL, LVTTL, CML,
PECL.
> >
> > - Familiar with high speed bus interfaces.
> >
> > - Knowledgeable with ASIC design flow and IO selection process.
> >
> > - Extensive use of SPICE and IBIS to simulate signal integrity for the
>high
> > speed board.
> >
> > - Experience with QUAD like tools to sign off PCB layout designs.
> >
> > - Multi-gigabit board design and EMI/EMC containment techniques.
> >
> > - Defined impedance controlled PCB stack-ups and familiar with
fabrication
> > process and backplane designs.
> >
> > - MSEE or PhD.
> >
> > - 8 + year's experience in signal integrity.
> >
> >
> >
> > ---------------------------------
> > Do You Yahoo!?
> > Yahoo! Buzz Index - Spot the hottest trends in music, movies,and more.
> >
> > ------------------------------------------------------------------
> > To unsubscribe from si-list:
> > si-list-request@xxxxxxxxxxxxx with 'unsubscribe' in the Subject field
> > For help:
> > si-list-request@xxxxxxxxxxxxx with 'help' in the Subject field
> >
> > List archives are viewable at:
>http://www.freelists.org/archives/si-list
> > Old list archives are viewable at: http://www.qsl.net/wb6tpu
> >
> >
>
>
>__________________________________________________
>Do You Yahoo!?
>Spot the hottest trends in music, movies, and more.
>http://buzz.yahoo.com/
>------------------------------------------------------------------
>To unsubscribe from si-list:
>si-list-request@xxxxxxxxxxxxx with 'unsubscribe' in the Subject field
>For help:
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>
>List archives are viewable at:
http://www.freelists.org/archives/si-list
>
>Old list archives are viewable at: http://www.qsl.net/wb6tpu
>
>
>------------------------------
>
>From: Michael Nudelman <mnudelman@xxxxxxxxxxx>
>Subject: [SI-LIST] Re: 1GHz clock needed, please share your info with
>Date: Mon, 18 Jun 2001 09:19:30 -0400
>
>
>Try Saronix
>
>-----Original Message-----
>From: Yu Wang [mailto:wangy_km@xxxxxxxxx]
>Sent: Saturday, June 16, 2001 6:17 PM
>To: si-list@xxxxxxxxxxxxx
>Subject: [SI-LIST] Re: 1GHz clock needed, please share your info with
>me.
>
>
>
>Hi, guys,
>I posted this query for several days, but
>unfortunately no answer. Could you all do me a faver
>to provide your comments? Thanks.
>
>regards,
>Yu
>--- Yu Wang <wangy_km@xxxxxxxxx> wrote:
> > Hi, gurus out of there,
> > I need a 1GHz clock generator and prefer that it's
> > best to be a single chip and cheap. The jitter
> > feature
> > is not very critical, 200ps is good enough.
> > Please give me an idea. Thank you.
> > all comments are highly appreciated.
> >
> > Yu Wang
> >
> > =====
> >
> >
> > __________________________________________________
> > Do You Yahoo!?
> > Get personalized email addresses from Yahoo! Mail -
> > only $35
> > a year! http://personal.mail.yahoo.com/
> >
>------------------------------------------------------------------
> > To unsubscribe from si-list:
> > si-list-request@xxxxxxxxxxxxx with 'unsubscribe' in
> > the Subject field
> > For help:
> > si-list-request@xxxxxxxxxxxxx with 'help' in the
> > Subject field
> >
> > List archives are viewable at:
> > http://www.freelists.org/archives/si-list
> > Old list archives are viewable at:
> > http://www.qsl.net/wb6tpu
> >
> >
>
>
>=====
>
>
>__________________________________________________
>Do You Yahoo!?
>Spot the hottest trends in music, movies, and more.
>http://buzz.yahoo.com/
>------------------------------------------------------------------
>To unsubscribe from si-list:
>si-list-request@xxxxxxxxxxxxx with 'unsubscribe' in the Subject field
>For help:
>si-list-request@xxxxxxxxxxxxx with 'help' in the Subject field
>
>List archives are viewable at:
http://www.freelists.org/archives/si-list
>
>Old list archives are viewable at: http://www.qsl.net/wb6tpu
>
>
>------------------------------
>
>From: rajat.chauhan@xxxxxx
>Date: Mon, 18 Jun 2001 19:52:23 +0530
>Subject: [SI-LIST] measuring Hi-Z and Lo-Z state
>
>
>Hello Ivor,
> I don't know if there is any such Std. method for measuring Hi-Z or
>Lo-Z state .Generaly vendors specify the way they have used to measure
>them, along with their specs. For one such method you can refer chapter
>6, section 6.2(AC Outputs) of book Application-Specific Integrated
>Circuits by Michael John Sebastian Smith. You can find this book at
>www.dacafe.com .
>
>regards
>Rajat
> >
> > Hi,
> >
> > I am running hspice simulation on a bidirectional IO buffer provided by
> > my vendor. I am wondering whether there is a standard circuit
> > configuration to measure the Hi-Z and the Lo-Z state of the buffer? I
> > want to make sure that bus contention does not happen for this
> > interface.
> >
> > Ivor.
> > --
> > **************************************************************
> > Ivor Ting Email: ivor.ting@xxxxxxxxxxx
> > ASIC Development, Alcatel CID Phone: (604)-453-3208
> > Suite 400-4190 Still Creek Drive Fax : (604)-421-2644
> > Burnaby, B.C., Canada, V5C 6C6 Web : www.cid.alcatel.com
> > **************************************************************
> >
> >
> > ------------------------------------------------------------------
>
>
>
>
>
>
>
>
>------------------------------
>
>From: "BIBICHA" <f_bouchra@xxxxxxxxx>
>Subject: [SI-LIST] Improve the heat on a PCB
>Date: Mon, 18 Jun 2001 13:08:42 -0400
>
>
>Hi All:
>
>I am just wondering if anybody know how to improve heat dissipation on a
>PCB. That would include additional layers, more copper...
>
>Any help is greatly appreciated
>
>Thanks
>Bouchra
>
>
>_________________________________________________________
>Do You Yahoo!?
>Get your free @yahoo.com address at http://mail.yahoo.com
>
>
>------------------------------
>
>From: "Zabinski, Patrick J." <zabinski.patrick@xxxxxxxx>
>Subject: [SI-LIST] Re: Improve the heat on a PCB
>Date: Mon, 18 Jun 2001 12:03:53 -0500
>
>
>A couple of ideas to consider:
>
>* Flood the outer surfaces with (grounded) copper, and
>expose as much of it as possible. Use soldermask
>sparingly, thus exposing the copper, which will in turn
>radiate more heat.
>
>* Use MANY vias to bring the heat from the hotter parts
>down to the inner planes. Then, use thick planes to
>spread the heat across the board.
>
>* If possible, thermally-connect the planes to external
>devices. For example, if you can, bring the ground planes
>to the outer board edges, expose the planes, and have
>the planes make contact to metal card rails, thus transfering
>the heat to the enclosure.
>
>In brief, try to find as many and as big of metallic path
>from the main heat sources to the outside as possible.
>
>Pat
>
> >
> >
> > Hi All:
> >
> > I am just wondering if anybody know how to improve heat
> > dissipation on a
> > PCB. That would include additional layers, more copper...
> >
> > Any help is greatly appreciated
> >
> > Thanks
> > Bouchra
> >
> >
>
>------------------------------
>
>Date: Mon, 18 Jun 2001 13:59:41 -0400
>From: Michael Baxter <baxter@xxxxxxxx>
>Subject: [SI-LIST] Hspice core dump
>
>
>Hello to everyone,
>
>I've been having a problem recently with Hspice causing
>a core dump when I run a set of encrypted models (the
>encryption may or may not be a factor). In the recent
>past I had a similar problem with another vendor's models
>but found something simple (like a node name it did not
>like) that was causing the dump.
>
>Has anyone seen a similar problem? Any suggestions on
>where to look?
>
>Thanks,
>
>- Michael
>
>+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~+
>| Michael Baxter e-mail: baxter@xxxxxxxx |
>| Principal SI Engineer |
>| NESA, Inc. http://www.nesa.com/ |
>| 5 LAN Drive ~ Suite 200 Tel +1.978.392-8787 |
>| Westford, MA 01886 USA Fax +1.978.392-8686 |
>+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~+
>
>
>------------------------------
>
>Date: Mon, 18 Jun 2001 11:06:23 -0700
>From: Scott McMorrow <scott@xxxxxxxxxxxxxxxx>
>Subject: [SI-LIST] Re: Hspice core dump
>
>
>Michael,
>
>Are you running 2000.4 or 2000.2?
>We're finding lots of little issues with 2000.4 here.
>
>scott
>
>
>--
>Scott McMorrow
>Principal Engineer
>SiQual, Signal Quality Engineering
>18735 SW Boones Ferry Road
>Tualatin, OR 97062-3090
>(503) 885-1231
>http://www.siqual.com
>
>
>Michael Baxter wrote:
>
> > Hello to everyone,
> >
> > I've been having a problem recently with Hspice causing
> > a core dump when I run a set of encrypted models (the
> > encryption may or may not be a factor). In the recent
> > past I had a similar problem with another vendor's models
> > but found something simple (like a node name it did not
> > like) that was causing the dump.
> >
> > Has anyone seen a similar problem? Any suggestions on
> > where to look?
> >
> > Thanks,
> >
> > - Michael
> >
> > +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~+
> > | Michael Baxter e-mail: baxter@xxxxxxxx |
> > | Principal SI Engineer |
> > | NESA, Inc. http://www.nesa.com/ |
> > | 5 LAN Drive ~ Suite 200 Tel +1.978.392-8787 |
> > | Westford, MA 01886 USA Fax +1.978.392-8686 |
> > +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~+
> >
> > ------------------------------------------------------------------
> > To unsubscribe from si-list:
> > si-list-request@xxxxxxxxxxxxx with 'unsubscribe' in the Subject field
> > For help:
> > si-list-request@xxxxxxxxxxxxx with 'help' in the Subject field
> >
> > List archives are viewable
> at: http://www.freelists.org/archives/si-list
> > Old list archives are viewable at: http://www.qsl.net/wb6tpu
> >
>
>
>
>
>------------------------------
>
>From: "chen, jinhua" <chen_jinhua@xxxxxxx>
>Subject: [SI-LIST] Re: Hspice core dump
>Date: Mon, 18 Jun 2001 14:08:17 -0400
>
>
>Hi, Michael
>
>Most of the core dumps I had were caused by the ^M in the
>end of each line. Did you check the format the encrypted
>models? If it is in DOS format, you have to change it to
>UNIX format.
>
>Good luck!
>
>Jinhua
>
>-----Original Message-----
>From: Michael Baxter [mailto:baxter@xxxxxxxx]
>Sent: Monday, June 18, 2001 2:00 PM
>To: si-list@xxxxxxxxxxxxx
>Subject: [SI-LIST] Hspice core dump
>
>
>
>Hello to everyone,
>
>I've been having a problem recently with Hspice causing
>a core dump when I run a set of encrypted models (the
>encryption may or may not be a factor). In the recent
>past I had a similar problem with another vendor's models
>but found something simple (like a node name it did not
>like) that was causing the dump.
>
>Has anyone seen a similar problem? Any suggestions on
>where to look?
>
>Thanks,
>
>- Michael
>
>+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~+
>| Michael Baxter e-mail: baxter@xxxxxxxx |
>| Principal SI Engineer |
>| NESA, Inc. http://www.nesa.com/ |
>| 5 LAN Drive ~ Suite 200 Tel +1.978.392-8787 |
>| Westford, MA 01886 USA Fax +1.978.392-8686 |
>+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~+
>
>------------------------------------------------------------------
>To unsubscribe from si-list:
>si-list-request@xxxxxxxxxxxxx with 'unsubscribe' in the Subject field
>For help:
>si-list-request@xxxxxxxxxxxxx with 'help' in the Subject field
>
>List archives are viewable at:
http://www.freelists.org/archives/si-list
>
>Old list archives are viewable at: http://www.qsl.net/wb6tpu
>
>
>------------------------------
>
>From: Vikas.Mishra@xxxxxxxxxx
>Date: Mon, 18 Jun 2001 14:08:54 +0500
>Subject: [SI-LIST] Re: Voltage rating of a Ceramic capacitor
>
>
>
>
>Hi Ravinder,
>
>X5R is a good choice for decoupling purpose as it has high dielectric
constant
>and temperature stability.
>Regarding voltage rating, the rule of thumb is >150% of Operating voltage.
As
>far as your application is considered 10V will be an appropriate choice.
>
>Thanks
>Vikas
>
>-----Original Message-----
>From: Ravinder Ajmani [mailto:ajmani@xxxxxxxxxx]
>Sent: Thursday, June 14, 2001 6:12 PM
>To: si-list@xxxxxxxxxxxxx
>Subject: [SI-LIST] Voltage rating of a Ceramic capacitor
>
>
>I have been asked to replace Tantalum bulk capacitor in a design with a
>suitable Ceramic capacitor. The Ceramic capacitor is X5R type, which I
>believe is more stable than Y5V. However, its voltage rating being
>6.3V, I
>am not feeling very comfortable to use it in the 5V application. Can
>anyone advise me about the minimum voltage rating I should have for a
>bulk
>Ceramic capacitor in a 5V application.
>
>Regards, Ravinder
>PCB Development and Design Department
>IBM Corporation
>Email: ajmani@xxxxxxxxxx
>
>
>
>------------------------------
>
>From: "Doug McKean" <dmckean@xxxxxxxxxxxxxxx>
>Subject: [SI-LIST] FYI: Solder ...
>Date: Mon, 18 Jun 2001 11:44:28 -0700
>
>
>Thought is was an interesting article to pass along ...
>
> http://www.tms.org/pubs/journals/JOM/9605/McCormack-9605.html
>
>- Doug McKean
>
>
>
>
>------------------------------
>
>From: MikonCons@xxxxxxx
>Date: Mon, 18 Jun 2001 15:35:47 EDT
>Subject: [SI-LIST] Re: SI Position Open READ THIS!!!!
>
>Bo:
>
>Please don't take personal offense at the following. Most of your comments
>are on target; however, there are several of us "older dawgs" who have been
>providing guidance and education/tutorials in SI long before 1990. For the
>microwave dudes, transmission line characteristics and their associated
>impedance transformations versus frequency were standard fare to even be in
>the design area. I used SI techniques in 1961 to design a folded resonant
>cavity S-band (2.4 GHz), low-noise (1.2 dB noise figure) receiver that was
>1/8-inch thick and one-inch square. I used two layers of teflon-fiberglass
>PCB material to build a narrowband signal frequency filter at 2.4 GHz, a
>2.397 GHz local oscillator (LO) tank, and a 30 MHz intermediate frequency
>(IF) tank. I used a single Tunnel diode that operated at 300 UA at 375 mVdc
>to achieve 14 dB signal plus down-conversion gain. The effort was for the
>USAF and not for comercialization.
>
>"SI" has only recently become familiar to the digital "ones and zeros"
crowd
>that now realize that they must learn analog techniques to rise to the next
>level of electronic systems education. The market volume demand for
>communications networks is of course the primary driver today.
>
>My particular strength that got me into the currently popular digital SI
>field was EMI. As many now know, radiated emissions problems usually have
>their roots in poor SI designs on PCBs.
>
>Just my 2 cents.
>
>Mike
>
>Michael L. Conn
>Owner/Principal Consultant
>Mikon Consulting
>(408)727-5697
>
> *** Serving Your Needs with technical Excellence ***
>
>
>
>------------------------------
>
>Date: Mon, 18 Jun 2001 13:51:05 -0700
>From: "Dr. John L. Prince" <prince@xxxxxxxxxxxxxxx>
>Subject: [SI-LIST] Re: SI Position Open READ THIS!!!!
>
>
>The temptation is just too great!! The endeavor we call SI now has been
>around possibly since the 50's, at major computer companies (or maybe just
>at one major computer company). I first developed and taught a
>university-level class (at Clemson University) which included "SI" elements
>in 1977--it was in fact a class in high speed digital electronics, so it
>included the circuit characteristics as well it must in this area. Bill
>Blood, thanks for help from your book! In 1983 the situation was becoming
>more serious, and here at Arizona we started a class in packaging which
>included "SI" elements. In 1984 we received major funding from SRC (which
>we still have, nearly 20 years later) to develop the science and algorithms
>behind what you now call "SI". Around 200 papers dating back to 1986, and
>numerous graduate students(dating back to 1986), have come out of this
>effort. Since 1990 or so there are other university programs (but not
>very many) which also address this area.
>
>So, there is little new under the sun today, just new names for things.
>And, just more fun to be had in a neat field. John Prince
>
>At 06:45 PM 06/15/2001 -0700, you wrote:
> >
> >Hi Esther,
> >
> >I am not sure if you are aware but Signal Integrity did show up until
> 94-95.
> >The only person to satisfy your requirements is Howard Johnson aka author
of
> >first book on SI "Book of Black Magic". What I am trying to say is that
> your
> >post will make some people laugh. Don't worry you are not the first one
> with
> >similar post. What you should have wrought is "8 years of high speed PCB
>board
> >design with emphasis on signal integrity". That would be more belivable.
> >The SI wasn't issue at lower speeds. It has shown up in last few years
as a
> >mayor issue. I have been working on SI and I can tell you there aren't
that
> >many people who really know SI. You should look for a person who has
>designed
> >whole lot of backplanes and who has done SI simulations on their own (not
> >someone who got other people to do it for them).
> >
> >I hope this helps you. And I hope you find right person for the job.
> >
> >
> >Regards,
> >Bo
> >
> >p.s. If you need help being more specific in your search feel free to
> contact
> >me.
> >p.p.s. I am not looking for a job and I probably wouldn't fit your
> >qualifications. I am just trying to help.
> >
> >--- esther williams <estherw2000@xxxxxxxxx> wrote:
> >>
> >> Hello - The following is a SI position at an Optical Data Networking
start
> >> up.
> >>
> >> Please contact: Esther at ewilliams@xxxxxxxxxxxx for more information.
> >>
> >> Title: Senior Signal Integrity Engineer
> >>
> >> Location: Mountain View, CA
> >>
> >> Job Description:
> >>
> >> - Specify, simulate, design and analyze high speed interfaces for data
> >> networking systems.
> >>
> >> - Verification of actual hardware and confirm the simulations results
to
> >> guarantee integrity of all the high speed interfaces.
> >>
> >> - Generate guide lines for board designers and layout designers for the
>high
> >> speed routing.
> >>
> >> - Setup process to sign off layouts for PCB fabs.
> >>
> >> Position Requirements:
> >>
> >> - Experience with high speed IOs like LVDS, HSTL, SSTL, LVTTL, CML,
PECL.
> >>
> >> - Familiar with high speed bus interfaces.
> >>
> >> - Knowledgeable with ASIC design flow and IO selection process.
> >>
> >> - Extensive use of SPICE and IBIS to simulate signal integrity for the
> high
> >> speed board.
> >>
> >> - Experience with QUAD like tools to sign off PCB layout designs.
> >>
> >> - Multi-gigabit board design and EMI/EMC containment techniques.
> >>
> >> - Defined impedance controlled PCB stack-ups and familiar with
fabrication
> >> process and backplane designs.
> >>
> >> - MSEE or PhD.
> >>
> >> - 8 + year's experience in signal integrity.
> >>
> >>
> >>
> >> ---------------------------------
> >> Do You Yahoo!?
> >> Yahoo! Buzz Index - Spot the hottest trends in music, movies,and more.
> >>
> >> ------------------------------------------------------------------
> >> To unsubscribe from si-list:
> >> si-list-request@xxxxxxxxxxxxx with 'unsubscribe' in the Subject field
> >> For help:
> >> si-list-request@xxxxxxxxxxxxx with 'help' in the Subject field
> >>
> >> List archives are viewable at:
>http://www.freelists.org/archives/si-list
> >> Old list archives are viewable at: http://www.qsl.net/wb6tpu
> >>
> >>
> >
> >
> >__________________________________________________
> >Do You Yahoo!?
> >Spot the hottest trends in music, movies, and more.
> >http://buzz.yahoo.com/
> >------------------------------------------------------------------
> >To unsubscribe from si-list:
> >si-list-request@xxxxxxxxxxxxx with 'unsubscribe' in the Subject field
> >For help:
> >si-list-request@xxxxxxxxxxxxx with 'help' in the Subject field
> >
> >List archives are viewable
> at: http://www.freelists.org/archives/si-list
> >Old list archives are viewable at: http://www.qsl.net/wb6tpu
> >
> >
> >
>John L. Prince, PhD
>Professor
>Director,Center for Electronic Packaging Research
>Department of Electrical and Computer Engineering
>University of Arizona
>1230 E. Speedway
>Tucson, AZ 85721-104
>prince@xxxxxxxxxxxxxxx
>520-621-6187
>520-621-2999(FAX)
>
>------------------------------
>
>From: "Yibing Tang" <ytang@xxxxxxxxxxxxxxxxx>
>Subject: [SI-LIST] Re: SI Position Open READ THIS!!!!
>Date: Mon, 18 Jun 2001 14:16:09 -0700
>
>
>That's too hot. Anyway, I learn the "history" of SI.
> From my understanding, SI just means digital guys are now getting familiar
>with some concepts of microwave technology. Yibing
>
>
>-----Original Message-----
>From: si-list-bounce@xxxxxxxxxxxxx
>[mailto:si-list-bounce@xxxxxxxxxxxxx]On Behalf Of Dr. John L. Prince
>Sent: Monday, June 18, 2001 1:51 PM
>To: si-list@xxxxxxxxxxxxx
>Subject: [SI-LIST] Re: SI Position Open READ THIS!!!!
>
>
>
>The temptation is just too great!! The endeavor we call SI now has been
>around possibly since the 50's, at major computer companies (or maybe just
>at one major computer company). I first developed and taught a
>university-level class (at Clemson University) which included "SI" elements
>in 1977--it was in fact a class in high speed digital electronics, so it
>included the circuit characteristics as well it must in this area. Bill
>Blood, thanks for help from your book! In 1983 the situation was becoming
>more serious, and here at Arizona we started a class in packaging which
>included "SI" elements. In 1984 we received major funding from SRC (which
>we still have, nearly 20 years later) to develop the science and algorithms
>behind what you now call "SI". Around 200 papers dating back to 1986, and
>numerous graduate students(dating back to 1986), have come out of this
>effort. Since 1990 or so there are other university programs (but not
>very many) which also address this area.
>
>So, there is little new under the sun today, just new names for things.
>And, just more fun to be had in a neat field. John Prince
>
>At 06:45 PM 06/15/2001 -0700, you wrote:
> >
> >Hi Esther,
> >
> >I am not sure if you are aware but Signal Integrity did show up until
>94-95.
> >The only person to satisfy your requirements is Howard Johnson aka author
>of
> >first book on SI "Book of Black Magic". What I am trying to say is that
>your
> >post will make some people laugh. Don't worry you are not the first one
>with
> >similar post. What you should have wrought is "8 years of high speed PCB
>board
> >design with emphasis on signal integrity". That would be more belivable.
> >The SI wasn't issue at lower speeds. It has shown up in last few years
as
>a
> >mayor issue. I have been working on SI and I can tell you there aren't
>that
> >many people who really know SI. You should look for a person who has
>designed
> >whole lot of backplanes and who has done SI simulations on their own (not
> >someone who got other people to do it for them).
> >
> >I hope this helps you. And I hope you find right person for the job.
> >
> >
> >Regards,
> >Bo
> >
> >p.s. If you need help being more specific in your search feel free to
>contact
> >me.
> >p.p.s. I am not looking for a job and I probably wouldn't fit your
> >qualifications. I am just trying to help.
> >
> >--- esther williams <estherw2000@xxxxxxxxx> wrote:
> >>
> >> Hello - The following is a SI position at an Optical Data Networking
>start
> >> up.
> >>
> >> Please contact: Esther at ewilliams@xxxxxxxxxxxx for more information.
> >>
> >> Title: Senior Signal Integrity Engineer
> >>
> >> Location: Mountain View, CA
> >>
> >> Job Description:
> >>
> >> - Specify, simulate, design and analyze high speed interfaces for data
> >> networking systems.
> >>
> >> - Verification of actual hardware and confirm the simulations results
to
> >> guarantee integrity of all the high speed interfaces.
> >>
> >> - Generate guide lines for board designers and layout designers for the
>high
> >> speed routing.
> >>
> >> - Setup process to sign off layouts for PCB fabs.
> >>
> >> Position Requirements:
> >>
> >> - Experience with high speed IOs like LVDS, HSTL, SSTL, LVTTL, CML,
PECL.
> >>
> >> - Familiar with high speed bus interfaces.
> >>
> >> - Knowledgeable with ASIC design flow and IO selection process.
> >>
> >> - Extensive use of SPICE and IBIS to simulate signal integrity for the
>high
> >> speed board.
> >>
> >> - Experience with QUAD like tools to sign off PCB layout designs.
> >>
> >> - Multi-gigabit board design and EMI/EMC containment techniques.
> >>
> >> - Defined impedance controlled PCB stack-ups and familiar with
>fabrication
> >> process and backplane designs.
> >>
> >> - MSEE or PhD.
> >>
> >> - 8 + years experience in signal integrity.
> >>
> >>
> >>
> >> ---------------------------------
> >> Do You Yahoo!?
> >> Yahoo! Buzz Index - Spot the hottest trends in music, movies,and more.
> >>
> >> ------------------------------------------------------------------
> >> To unsubscribe from si-list:
> >> si-list-request@xxxxxxxxxxxxx with 'unsubscribe' in the Subject field
> >> For help:
> >> si-list-request@xxxxxxxxxxxxx with 'help' in the Subject field
> >>
> >> List archives are viewable at:
>http://www.freelists.org/archives/si-list
> >> Old list archives are viewable at: http://www.qsl.net/wb6tpu
> >>
> >>
> >
> >
> >__________________________________________________
> >Do You Yahoo!?
> >Spot the hottest trends in music, movies, and more.
> >http://buzz.yahoo.com/
> >------------------------------------------------------------------
> >To unsubscribe from si-list:
> >si-list-request@xxxxxxxxxxxxx with 'unsubscribe' in the Subject field
> >For help:
> >si-list-request@xxxxxxxxxxxxx with 'help' in the Subject field
> >
> >List archives are viewable at:
>http://www.freelists.org/archives/si-list
> >Old list archives are viewable at: http://www.qsl.net/wb6tpu
> >
> >
> >
>John L. Prince, PhD
>Professor
>Director,Center for Electronic Packaging Research
>Department of Electrical and Computer Engineering
>University of Arizona
>1230 E. Speedway
>Tucson, AZ 85721-104
>prince@xxxxxxxxxxxxxxx
>520-621-6187
>520-621-2999(FAX)
>------------------------------------------------------------------
>To unsubscribe from si-list:
>si-list-request@xxxxxxxxxxxxx with 'unsubscribe' in the Subject field
>For help:
>si-list-request@xxxxxxxxxxxxx with 'help' in the Subject field
>
>List archives are viewable at:
http://www.freelists.org/archives/si-list
>Old list archives are viewable at: http://www.qsl.net/wb6tpu
>
>
>
>------------------------------
>
>From: "Kai, Francis" <francis.kai@xxxxxxxxx>
>Subject: [SI-LIST] Re: SI Position Open READ THIS!!!!
>Date: Mon, 18 Jun 2001 14:21:27 -0700
>
>
>After Mike Conn and Prof. Prince have addressed the history of SI, I would
>suggest the original advertiser, Optical Data Networking, or other hiring
>companies, to put down the knowledge of the history of SI as one of the
>"Position Requirement".
>
>I used to be a teacher and I know it is very important for a student or a
>working engineer to know the history of his/her own field. The knowledge
>will help the student or engineer to know the progress and development of
>this particular branch of science. When a complicated problem pops up in
>his/her lab or simulation run, he/she can trace this problem to the related
>area and solve the problem. I am happy to see there are many gurus in the
>[SI-LIST] to help younger engineers with history to solve their problems.
>
>Signal integrity is a "neat field", as pointed out by Prof. Prince. Working
>engineers need continuous help from professional consultants and gurus to
>learn this field.
>
>Francis Kai
>
>-----Original Message-----
>From: Dr. John L. Prince [mailto:prince@xxxxxxxxxxxxxxx]
>Sent: Monday, June 18, 2001 1:51 PM
>To: si-list@xxxxxxxxxxxxx
>Subject: [SI-LIST] Re: SI Position Open READ THIS!!!!
>
>
>
>The temptation is just too great!! The endeavor we call SI now has been
>around possibly since the 50's, at major computer companies (or maybe just
>at one major computer company). I first developed and taught a
>university-level class (at Clemson University) which included "SI" elements
>in 1977--it was in fact a class in high speed digital electronics, so it
>included the circuit characteristics as well it must in this area. Bill
>Blood, thanks for help from your book! In 1983 the situation was becoming
>more serious, and here at Arizona we started a class in packaging which
>included "SI" elements. In 1984 we received major funding from SRC (which
>we still have, nearly 20 years later) to develop the science and algorithms
>behind what you now call "SI". Around 200 papers dating back to 1986, and
>numerous graduate students(dating back to 1986), have come out of this
>effort. Since 1990 or so there are other university programs (but not
>very many) which also address this area.
>
>So, there is little new under the sun today, just new names for things.
>And, just more fun to be had in a neat field. John Prince
>
>At 06:45 PM 06/15/2001 -0700, you wrote:
> >
> >Hi Esther,
> >
> >I am not sure if you are aware but Signal Integrity did show up until
>94-95.
> >The only person to satisfy your requirements is Howard Johnson aka author
>of
> >first book on SI "Book of Black Magic". What I am trying to say is that
>your
> >post will make some people laugh. Don't worry you are not the first one
>with
> >similar post. What you should have wrought is "8 years of high speed PCB
>board
> >design with emphasis on signal integrity". That would be more belivable.
> >The SI wasn't issue at lower speeds. It has shown up in last few years
as
>a
> >mayor issue. I have been working on SI and I can tell you there aren't
>that
> >many people who really know SI. You should look for a person who has
>designed
> >whole lot of backplanes and who has done SI simulations on their own (not
> >someone who got other people to do it for them).
> >
> >I hope this helps you. And I hope you find right person for the job.
> >
> >
> >Regards,
> >Bo
> >
> >p.s. If you need help being more specific in your search feel free to
>contact
> >me.
> >p.p.s. I am not looking for a job and I probably wouldn't fit your
> >qualifications. I am just trying to help.
> >
> >--- esther williams <estherw2000@xxxxxxxxx> wrote:
> >>
> >> Hello - The following is a SI position at an Optical Data Networking
>start
> >> up.
> >>
> >> Please contact: Esther at ewilliams@xxxxxxxxxxxx for more information.
> >>
> >> Title: Senior Signal Integrity Engineer
> >>
> >> Location: Mountain View, CA
> >>
> >> Job Description:
> >>
> >> - Specify, simulate, design and analyze high speed interfaces for data
> >> networking systems.
> >>
> >> - Verification of actual hardware and confirm the simulations results
to
> >> guarantee integrity of all the high speed interfaces.
> >>
> >> - Generate guide lines for board designers and layout designers for the
>high
> >> speed routing.
> >>
> >> - Setup process to sign off layouts for PCB fabs.
> >>
> >> Position Requirements:
> >>
> >> - Experience with high speed IOs like LVDS, HSTL, SSTL, LVTTL, CML,
PECL.
> >>
> >> - Familiar with high speed bus interfaces.
> >>
> >> - Knowledgeable with ASIC design flow and IO selection process.
> >>
> >> - Extensive use of SPICE and IBIS to simulate signal integrity for the
>high
> >> speed board.
> >>
> >> - Experience with QUAD like tools to sign off PCB layout designs.
> >>
> >> - Multi-gigabit board design and EMI/EMC containment techniques.
> >>
> >> - Defined impedance controlled PCB stack-ups and familiar with
>fabrication
> >> process and backplane designs.
> >>
> >> - MSEE or PhD.
> >>
> >> - 8 + year's experience in signal integrity.
> >>
> >>
> >>
> >> ---------------------------------
> >> Do You Yahoo!?
> >> Yahoo! Buzz Index - Spot the hottest trends in music, movies,and more.
> >>
> >> ------------------------------------------------------------------
> >> To unsubscribe from si-list:
> >> si-list-request@xxxxxxxxxxxxx with 'unsubscribe' in the Subject field
> >> For help:
> >> si-list-request@xxxxxxxxxxxxx with 'help' in the Subject field
> >>
> >> List archives are viewable at:
>http://www.freelists.org/archives/si-list
> >> Old list archives are viewable at: http://www.qsl.net/wb6tpu
> >>
> >>
> >
> >
> >__________________________________________________
> >Do You Yahoo!?
> >Spot the hottest trends in music, movies, and more.
> >http://buzz.yahoo.com/
> >------------------------------------------------------------------
> >To unsubscribe from si-list:
> >si-list-request@xxxxxxxxxxxxx with 'unsubscribe' in the Subject field
> >For help:
> >si-list-request@xxxxxxxxxxxxx with 'help' in the Subject field
> >
> >List archives are viewable at:
>http://www.freelists.org/archives/si-list
> >Old list archives are viewable at: http://www.qsl.net/wb6tpu
> >
> >
> >
>John L. Prince, PhD
>Professor
>Director,Center for Electronic Packaging Research
>Department of Electrical and Computer Engineering
>University of Arizona
>1230 E. Speedway
>Tucson, AZ 85721-104
>prince@xxxxxxxxxxxxxxx
>520-621-6187
>520-621-2999(FAX)
>------------------------------------------------------------------
>To unsubscribe from si-list:
>si-list-request@xxxxxxxxxxxxx with 'unsubscribe' in the Subject field
>For help:
>si-list-request@xxxxxxxxxxxxx with 'help' in the Subject field
>
>List archives are viewable at:
http://www.freelists.org/archives/si-list
>
>Old list archives are viewable at: http://www.qsl.net/wb6tpu
>
>
>
>
>------------------------------
>
>Date: Mon, 18 Jun 2001 14:43:23 -0700
>From: George James <george@xxxxxxxxxxxxxxxx>
>Subject: [SI-LIST] Re: SI Position Open READ THIS!!!!
>
>
>Some of us real old timers even remember the early days of ECL. SI has
>been around for a long time and for awhile it was a lost art. Really good
>to see the expertise be passe on with the increased need with todays
>lighting bolt edge rates and frequencies.
>
>At 01:51 PM 6/18/01 -0700, Dr. John L. Prince wrote:
>
> >The temptation is just too great!! The endeavor we call SI now has been
> >around possibly since the 50's, at major computer companies (or maybe
just
> >at one major computer company). I first developed and taught a
> >university-level class (at Clemson University) which included "SI"
elements
> >in 1977--it was in fact a class in high speed digital electronics, so it
> >included the circuit characteristics as well it must in this area. Bill
> >Blood, thanks for help from your book! In 1983 the situation was
becoming
> >more serious, and here at Arizona we started a class in packaging which
> >included "SI" elements. In 1984 we received major funding from SRC
(which
> >we still have, nearly 20 years later) to develop the science and
algorithms
> >behind what you now call "SI". Around 200 papers dating back to 1986,
and
> >numerous graduate students(dating back to 1986), have come out of this
> >effort. Since 1990 or so there are other university programs (but not
> >very many) which also address this area.
> >
> >So, there is little new under the sun today, just new names for things.
> >And, just more fun to be had in a neat field. John Prince
> >
> >At 06:45 PM 06/15/2001 -0700, you wrote:
> > >
> > >Hi Esther,
> > >
> > >I am not sure if you are aware but Signal Integrity did show up until
> > 94-95.
> > >The only person to satisfy your requirements is Howard Johnson aka
> author of
> > >first book on SI "Book of Black Magic". What I am trying to say is
that
> > your
> > >post will make some people laugh. Don't worry you are not the first
one
> > with
> > >similar post. What you should have wrought is "8 years of high speed
PCB
> >board
> > >design with emphasis on signal integrity". That would be more
belivable.
> > >The SI wasn't issue at lower speeds. It has shown up in last few
> years as a
> > >mayor issue. I have been working on SI and I can tell you there
> aren't that
> > >many people who really know SI. You should look for a person who has
> >designed
> > >whole lot of backplanes and who has done SI simulations on their own
(not
> > >someone who got other people to do it for them).
> > >
> > >I hope this helps you. And I hope you find right person for the job.
> > >
> > >
> > >Regards,
> > >Bo
> > >
> > >p.s. If you need help being more specific in your search feel free to
> > contact
> > >me.
> > >p.p.s. I am not looking for a job and I probably wouldn't fit your
> > >qualifications. I am just trying to help.
> > >
> > >--- esther williams <estherw2000@xxxxxxxxx> wrote:
> > >>
> > >> Hello - The following is a SI position at an Optical Data Networking
> start
> > >> up.
> > >>
> > >> Please contact: Esther at ewilliams@xxxxxxxxxxxx for more
information.
> > >>
> > >> Title: Senior Signal Integrity Engineer
> > >>
> > >> Location: Mountain View, CA
> > >>
> > >> Job Description:
> > >>
> > >> - Specify, simulate, design and analyze high speed interfaces for
data
> > >> networking systems.
> > >>
> > >> - Verification of actual hardware and confirm the simulations results
to
> > >> guarantee integrity of all the high speed interfaces.
> > >>
> > >> - Generate guide lines for board designers and layout designers for
the
> >high
> > >> speed routing.
> > >>
> > >> - Setup process to sign off layouts for PCB fabs.
> > >>
> > >> Position Requirements:
> > >>
> > >> - Experience with high speed IOs like LVDS, HSTL, SSTL, LVTTL, CML,
> PECL.
> > >>
> > >> - Familiar with high speed bus interfaces.
> > >>
> > >> - Knowledgeable with ASIC design flow and IO selection process.
> > >>
> > >> - Extensive use of SPICE and IBIS to simulate signal integrity for
the
> > high
> > >> speed board.
> > >>
> > >> - Experience with QUAD like tools to sign off PCB layout designs.
> > >>
> > >> - Multi-gigabit board design and EMI/EMC containment techniques.
> > >>
> > >> - Defined impedance controlled PCB stack-ups and familiar with
> fabrication
> > >> process and backplane designs.
> > >>
> > >> - MSEE or PhD.
> > >>
> > >> - 8 + year's experience in signal integrity.
> > >>
> > >>
> > >>
> > >> ---------------------------------
> > >> Do You Yahoo!?
> > >> Yahoo! Buzz Index - Spot the hottest trends in music, movies,and
more.
> > >>
> > >> ------------------------------------------------------------------
> > >> To unsubscribe from si-list:
> > >> si-list-request@xxxxxxxxxxxxx with 'unsubscribe' in the Subject field
> > >> For help:
> > >> si-list-request@xxxxxxxxxxxxx with 'help' in the Subject field
> > >>
> > >> List archives are viewable at:
> >http://www.freelists.org/archives/si-list
> > >> Old list archives are viewable at: http://www.qsl.net/wb6tpu
> > >>
> > >>
> > >
> > >
> > >__________________________________________________
> > >Do You Yahoo!?
> > >Spot the hottest trends in music, movies, and more.
> > >http://buzz.yahoo.com/
> > >------------------------------------------------------------------
> > >To unsubscribe from si-list:
> > >si-list-request@xxxxxxxxxxxxx with 'unsubscribe' in the Subject field
> > >For help:
> > >si-list-request@xxxxxxxxxxxxx with 'help' in the Subject field
> > >
> > >List archives are viewable
> > at: http://www.freelists.org/archives/si-list
> > >Old list archives are viewable at: http://www.qsl.net/wb6tpu
> > >
> > >
> > >
> >John L. Prince, PhD
> >Professor
> >Director,Center for Electronic Packaging Research
> >Department of Electrical and Computer Engineering
> >University of Arizona
> >1230 E. Speedway
> >Tucson, AZ 85721-104
> >prince@xxxxxxxxxxxxxxx
> >520-621-6187
> >520-621-2999(FAX)
> >------------------------------------------------------------------
> >To unsubscribe from si-list:
> >si-list-request@xxxxxxxxxxxxx with 'unsubscribe' in the Subject field
> >For help:
> >si-list-request@xxxxxxxxxxxxx with 'help' in the Subject field
> >
> >List archives are viewable at:
http://www.freelists.org/archives/si-list
> >Old list archives are viewable at: http://www.qsl.net/wb6tpu
> >
>
>
>------------------------------
>
>From: Robison Michael R CNIN <Robison_M@xxxxxxxxxxxxxx>
>Subject: [SI-LIST] Re: SI Position Open READ THIS!!!!
>Date: Mon, 18 Jun 2001 17:19:15 -0500
>
>
>i kinda get the feeling that its the other way around... a true SI guy is
a
>
>microwave guy who's turned digital. ;-) all the digital guys that pick up
>on a little microwave are just SI wannabe's.
>
>miker
>
>p.s. i'm a digital guy and the above is said tongue-in-cheek.
>
> > -----Original Message-----
> > From: Yibing Tang [SMTP:ytang@xxxxxxxxxxxxxxxxx]
> > Sent: Monday, June 18, 2001 4:16 PM
> > To: si-list@xxxxxxxxxxxxx
> > Subject: [SI-LIST] Re: SI Position Open READ THIS!!!!
> >
> >
> > That's too hot. Anyway, I learn the "history" of SI.
> > From my understanding, SI just means digital guys are now getting
familiar
> > with some concepts of microwave technology. Yibing
> >
> >
> > -----Original Message-----
> > From: si-list-bounce@xxxxxxxxxxxxx
> > [mailto:si-list-bounce@xxxxxxxxxxxxx]On Behalf Of Dr. John L. Prince
> > Sent: Monday, June 18, 2001 1:51 PM
> > To: si-list@xxxxxxxxxxxxx
> > Subject: [SI-LIST] Re: SI Position Open READ THIS!!!!
> >
> >
> >
> > The temptation is just too great!! The endeavor we call SI now has been
> > around possibly since the 50's, at major computer companies (or maybe
just
> > at one major computer company). I first developed and taught a
> > university-level class (at Clemson University) which included "SI"
> > elements
> > in 1977--it was in fact a class in high speed digital electronics, so it
> > included the circuit characteristics as well it must in this area. Bill
> > Blood, thanks for help from your book! In 1983 the situation was
becoming
> > more serious, and here at Arizona we started a class in packaging which
> > included "SI" elements. In 1984 we received major funding from SRC
(which
> > we still have, nearly 20 years later) to develop the science and
> > algorithms
> > behind what you now call "SI". Around 200 papers dating back to 1986,
and
> > numerous graduate students(dating back to 1986), have come out of this
> > effort. Since 1990 or so there are other university programs (but not
> > very many) which also address this area.
> >
> > So, there is little new under the sun today, just new names for things.
> > And, just more fun to be had in a neat field. John Prince
> >
> > At 06:45 PM 06/15/2001 -0700, you wrote:
> > >
> > >Hi Esther,
> > >
> > >I am not sure if you are aware but Signal Integrity did show up until
> > 94-95.
> > >The only person to satisfy your requirements is Howard Johnson aka
author
> > of
> > >first book on SI "Book of Black Magic". What I am trying to say is
that
> > your
> > >post will make some people laugh. Don't worry you are not the first
one
> > with
> > >similar post. What you should have wrought is "8 years of high speed
PCB
> > board
> > >design with emphasis on signal integrity". That would be more
belivable.
> > >The SI wasn't issue at lower speeds. It has shown up in last few years
> > as
> > a
> > >mayor issue. I have been working on SI and I can tell you there aren't
> > that
> > >many people who really know SI. You should look for a person who has
> > designed
> > >whole lot of backplanes and who has done SI simulations on their own
(not
> > >someone who got other people to do it for them).
> > >
> > >I hope this helps you. And I hope you find right person for the job.
> > >
> > >
> > >Regards,
> > >Bo
> > >
> > >p.s. If you need help being more specific in your search feel free to
> > contact
> > >me.
> > >p.p.s. I am not looking for a job and I probably wouldn't fit your
> > >qualifications. I am just trying to help.
> > >
> > >--- esther williams <estherw2000@xxxxxxxxx> wrote:
> > >>
> > >> Hello - The following is a SI position at an Optical Data Networking
> > start
> > >> up.
> > >>
> > >> Please contact: Esther at ewilliams@xxxxxxxxxxxx for more
information.
> > >>
> > >> Title: Senior Signal Integrity Engineer
> > >>
> > >> Location: Mountain View, CA
> > >>
> > >> Job Description:
> > >>
> > >> - Specify, simulate, design and analyze high speed interfaces for
data
> > >> networking systems.
> > >>
> > >> - Verification of actual hardware and confirm the simulations results
> > to
> > >> guarantee integrity of all the high speed interfaces.
> > >>
> > >> - Generate guide lines for board designers and layout designers for
the
> > high
> > >> speed routing.
> > >>
> > >> - Setup process to sign off layouts for PCB fabs.
> > >>
> > >> Position Requirements:
> > >>
> > >> - Experience with high speed IOs like LVDS, HSTL, SSTL, LVTTL, CML,
> > PECL.
> > >>
> > >> - Familiar with high speed bus interfaces.
> > >>
> > >> - Knowledgeable with ASIC design flow and IO selection process.
> > >>
> > >> - Extensive use of SPICE and IBIS to simulate signal integrity for
the
> > high
> > >> speed board.
> > >>
> > >> - Experience with QUAD like tools to sign off PCB layout designs.
> > >>
> > >> - Multi-gigabit board design and EMI/EMC containment techniques.
> > >>
> > >> - Defined impedance controlled PCB stack-ups and familiar with
> > fabrication
> > >> process and backplane designs.
> > >>
> > >> - MSEE or PhD.
> > >>
> > >> - 8 + years experience in signal integrity.
> > >>
> > >>
> > >>
> > >> ---------------------------------
> > >> Do You Yahoo!?
> > >> Yahoo! Buzz Index - Spot the hottest trends in music, movies,and
more.
> > >>
> > >> ------------------------------------------------------------------
> > >> To unsubscribe from si-list:
> > >> si-list-request@xxxxxxxxxxxxx with 'unsubscribe' in the Subject field
> > >> For help:
> > >> si-list-request@xxxxxxxxxxxxx with 'help' in the Subject field
> > >>
> > >> List archives are viewable at:
> > http://www.freelists.org/archives/si-list
> > >> Old list archives are viewable at: http://www.qsl.net/wb6tpu
> > >>
> > >>
> > >
> > >
> > >__________________________________________________
> > >Do You Yahoo!?
> > >Spot the hottest trends in music, movies, and more.
> > >http://buzz.yahoo.com/
> > >------------------------------------------------------------------
> > >To unsubscribe from si-list:
> > >si-list-request@xxxxxxxxxxxxx with 'unsubscribe' in the Subject field
> > >For help:
> > >si-list-request@xxxxxxxxxxxxx with 'help' in the Subject field
> > >
> > >List archives are viewable at:
> > http://www.freelists.org/archives/si-list
> > >Old list archives are viewable at: http://www.qsl.net/wb6tpu
> > >
> > >
> > >
> > John L. Prince, PhD
> > Professor
> > Director,Center for Electronic Packaging Research
> > Department of Electrical and Computer Engineering
> > University of Arizona
> > 1230 E. Speedway
> > Tucson, AZ 85721-104
> > prince@xxxxxxxxxxxxxxx
> > 520-621-6187
> > 520-621-2999(FAX)
> > ------------------------------------------------------------------
> > To unsubscribe from si-list:
> > si-list-request@xxxxxxxxxxxxx with 'unsubscribe' in the Subject field
> > For help:
> > si-list-request@xxxxxxxxxxxxx with 'help' in the Subject field
> >
> > List archives are viewable at:
> > http://www.freelists.org/archives/si-list
> > Old list archives are viewable at: http://www.qsl.net/wb6tpu
> >
> >
> > ------------------------------------------------------------------
> > To unsubscribe from si-list:
> > si-list-request@xxxxxxxxxxxxx with 'unsubscribe' in the Subject field
> > For help:
> > si-list-request@xxxxxxxxxxxxx with 'help' in the Subject field
> >
> > List archives are viewable at:
> > http://www.freelists.org/archives/si-list
> > Old list archives are viewable at: http://www.qsl.net/wb6tpu
> >
>
>------------------------------
>
>Subject: [SI-LIST] Re: Voltage rating of a Ceramic capacitor
>From: "Ravinder Ajmani" <ajmani@xxxxxxxxxx>
>Date: Mon, 18 Jun 2001 16:47:02 -0600
>
>
>
>I would like to thank all of you who responded to my query on Ceramic
>capacitor voltage rating. Based on the replies I received, I should choose
>a voltage rating of 2 times the application voltage.
>
>Regards, Ravinder
>PCB Development and Design Department
>IBM Corporation
>Email: ajmani@xxxxxxxxxx
>***************************************************************************
>Always do right. This will gratify some people and astonish the rest.
>.... Mark Twain
>
>
>------------------------------
>
>From: Ed Priest <Ed_Priest@xxxxxxxxxxxxxx>
>Subject: [SI-LIST] Re: Inductance of Via
>Date: Mon, 18 Jun 2001 16:16:27 -0700
>
>
>Does this mean that the equation I have for a single plate capacitor isn't
>valid either?
>
>Ed
>
>-----Original Message-----
>From: Tsuk, Michael [mailto:Michael.Tsuk@xxxxxxxxxx]
>Sent: Monday, June 11, 2001 7:38 AM
>To: si-list@xxxxxxxxxxxxx
>Cc: ytang@xxxxxxxxxxxxxxxxx
>Subject: [SI-LIST] Re: Inductance of Via
>
>
>
>Yibing Tang wrote:
>
> > I use a formula to calculate the inductance of through hole via,
> > L=5.08h[ln(4h/d)+1]
> > However, I find that it is not suitable for small ratio of h to d.
> From this
> > formula,if decrease the ratio, I could get very lower inductance, even
> > negative.
>
>It makes no sense to talk about the inductance of a via in isolation.
>None at all. Inductance is a quality of a loop of current; without
>knowing where your return path is, you can't get a meaningful value for
>the total inductance.
>
>In any case, it seems that your formula isn't applicable to vias; this
>was discussed back in March. See:
>
>http://www.qsl.net/wb6tpu/si-list/0117.html
>
> > My question is how far I can go to low the inductance.
>
>You have two main choices:
>
>1. Bring the return path vias closer to the signal via
>2. Shorten the length of the via
>
>The effect of the diameter is relatively weak.
>
>--
>Michael Tsuk
>Compaq AlphaServer Product Development
>(508) 467-4621
>------------------------------------------------------------------
>To unsubscribe from si-list:
>si-list-request@xxxxxxxxxxxxx with 'unsubscribe' in the Subject field
>For help:
>si-list-request@xxxxxxxxxxxxx with 'help' in the Subject field
>
>List archives are viewable at:
http://www.freelists.org/archives/si-list
>Old list archives are viewable at: http://www.qsl.net/wb6tpu
>
>
>------------------------------
>
>Date: Mon, 18 Jun 2001 23:45:18 +0100
>From: Mike Ventham <ventham@xxxxxxxxxxxxxxxxx>
>Subject: [SI-LIST] Re: SI Position Open READ THIS!!!!
>
>
>
>The same seems to go for EMC engineers. I have met many who are 'old'
>analog engineers!
>
>At 23:19 18/06/01, you wrote:
>
> >i kinda get the feeling that its the other way around... a true SI guy
is a
> >
> >microwave guy who's turned digital. ;-) all the digital guys that pick
up
> >on a little microwave are just SI wannabe's.
> >
> >miker
> >
> >p.s. i'm a digital guy and the above is said tongue-in-cheek.
> >
> >(snipped for bandwidth)
>
>Regards
>
>Mike
>________________________________________________________________
>| Mike Ventham - Vice-President Engineering, |
>| Quantic EMC Inc. Headquarters |
>| Croft House, Chilcompton, 191 Lombard Ave., Winnipeg,|
>| Somerset, UK, BA3 4JA Manitoba, Canada R3B 0X1 |
>| Tel: 44 (0)1761 232191 Tel: (204) 942 4000 |
>| Fax: 44 (0)7974 141685 Fax: (204) 957 1158 |
>| Mobile: 44 (0)7971 553260 |
>| Email: ventham@xxxxxxxxxxxxxxxxx http://www.quantic-emc.com |
>
>
>
>------------------------------
>
>From: RCSXC@xxxxxxx
>Date: Mon, 18 Jun 2001 21:24:12 EDT
>Subject: [SI-LIST] Re: Improve the heat on a PCB
>
>What exactly is your application? If you have transistor drivers on the
board
>then you must try to heat sink them properly. The technique depends upon
the
>driver. Don't attempt to bring the heat into the interior layers unless it
>goes onto a large plane like ground, that can be exposed on the outer
layers
>to air. You can also use heavier copper on the PCB. An application for a
>board that I'm working on must be able to handle 150 amps of current
through
>it, for safety the copper is 6 oz. Best idea is to get the heat out quickly
>if possible. Also make sure that you are not stressing components that
>generate the heat by running them too close to their maximum power limits.
>Many ICs (including regulators) will thermally turn off if their junction
>temps exceed about 150 C.
>
>
>
>------------------------------
>
>End of si-list Digest V1 #27
>****************************
------------------------------------------------------------------
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------------------------------
Subject: [SI-LIST] Crosstalk between different layers
From: "Roberto Carretta" <rcarrett@xxxxxxxxxxxxx>
Date: Thu, 21 Jun 2001 15:46:41 +0200
Hi all,
I'm investigating this configuration in order to estimate the crosstalk
between L2 and L3.
L1 ------------- Plane (GND)
L2 --- signal
L3 --- signal
L4 ------------- Plane (Power)
My target is to obtain a minimum spacing between the two layers that allow a
maximum
crosstalk level (for example < 5%).
I'm wondering if I can use the H.Johnson book formula :
crosstalk < 1/[1+(D/H)^2].
If yes, assuming a ground-signal distance of 5 mils and a signal-signal
distance of 20 mils,
which is the value I have to use for H?
And if one signal layer is 90 degree routed, there is any difference?
In H.Johnson book section 5.8.5 (ten-layer stack) there is a similar
configuration:
the crosstalk between layers 4 and 6 is determined by the ratio of
separation to ground plane
height. But I don't understood how the geometric average height of 0.007
inch is calculated.
Thanks in advance.
Roberto Carretta.
------------------------------
Date: Wed, 20 Jun 2001 10:27:27 -0600
From: "Mark Alexander" <Mark.Alexander@xxxxxxxxxx>
Subject: [SI-LIST] Re: Voltage rating of a Ceramic capacitor
Harold,
I'd be very interested in your reasons for recommending against Z5U.
Thanks,
Mark Alexander
HaroldLSJ@xxxxxxx wrote:
> Ravinder,
>
> I must correct the misinformation you have received concerning the voltage
> rating of a ceramic capacitor and in particular for an X7R type
dielectric.
>
> First, ALL ceramic capacitors are tested to 2.5 times rated voltage so
your
> 6.3V rating has been 100% tested to 15.75 volts. Further, the typical X7R
> MLC (multilayer capacitor) will not breakdown until you reach a voltage
above
> 500V! The typical breakdown voltage I see is in the 500V to 800V range!
>
> Second, the voltage coefficient for X7R caps at ten (10V) volts is less
than
> a negative 5% change in capacitance value and at five (5V) volts it is
less
> than a negative 2% change in capacitance so this will not be a problem.
>
> Third, the typical temperature coefficient for X7R for this voltage range
> will not change the capacitance value by more than a negative fifteen
(15%)
> percent from -55C to +125C and is most likely to be less than -10%.
>
> Fourth, the biggest factor from a SI standpoint is the change in
capacitance
> value with frequency. This should be qualified on a part by part basis.
The
> typical X7R will drop ten (10%) percent of its value from zero to 1MHz so
get
> a good high frequency gain/phase meter and compare your tantalum and the
X7R
> you plan to use then adjust accordingly. If your frequency is extremely
> high, consider using a porcelain microwave cap. An NPO cap has almost
zero
> capacitance drop across this same frequency span.
>
> Remember an MLC is a miniature thick film hybrid circuit so test and mount
> the cap with the plates normal (vertical) to the PCB trace.
>
> Finally, ceramic caps like tantalums usually fail by shorting. If you
> require high reliability, then request the lot be HALT (highly accelerated
> life testing) qualified which is usually a maximum failure rate of between
5
> to 8 caps out of 55 tested from the lot you are interested in buying.
For
> extreme high reliability (zero failures), have the caps 100% HALT sorted.
> HALT testing will always find more failures than Mil testing. X7R will
> always have a higher reliability than NPO and don't use Z5U or Y5V. There
is
> not enough room here to discuss this further so email me direct if you
need
> more info on reliability.
>
> Harold L. Snyder, Jr.
> Scientist & Consultant
>
> Begin Included Message:
> ==========================
>
> > Subj: [SI-LIST] Voltage rating of a Ceramic capacitor
> > Date: 6/14/2001 5:13:41 PM Central Daylight Time
> > From: ajmani@xxxxxxxxxx (Ravinder Ajmani)
> > Sender: si-list-bounce@xxxxxxxxxxxxx
> > Reply-to: si-list@xxxxxxxxxxxxx
> > To: si-list@xxxxxxxxxxxxx
> >
> >
> >
> > I have been asked to replace Tantalum bulk capacitor in a design with a
> > suitable Ceramic capacitor. The Ceramic capacitor is X5R type, which I
> > believe is more stable than Y5V. However, its voltage rating being
6.3V, I
> > am not feeling very comfortable to use it in the 5V application. Can
> > anyone advise me about the minimum voltage rating I should have for a
bulk
> > Ceramic capacitor in a 5V application.
> >
> > Regards, Ravinder
> > PCB Development and Design Department
> > IBM Corporation
> > Email: ajmani@xxxxxxxxxx
> >
***************************************************************************
> > Always do right. This will gratify some people and astonish the rest.
> > .... Mark Twain
> >
> >
>
> ==========================
> End Included Message.
>
> ------------------------------------------------------------------
> To unsubscribe from si-list:
> si-list-request@xxxxxxxxxxxxx with 'unsubscribe' in the Subject field
> For help:
> si-list-request@xxxxxxxxxxxxx with 'help' in the Subject field
>
> List archives are viewable at:
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> Old list archives are viewable at: http://www.qsl.net/wb6tpu
>
------------------------------
Date: Wed, 20 Jun 2001 10:29:42 -0600
From: "Mark Alexander" <Mark.Alexander@xxxxxxxxxx>
Subject: [SI-LIST] Re: Voltage rating of a Ceramic capacitor
oops! sorry bout that.
------------------------------
From: "Wilson, Mary" <MWilson@xxxxxxxxxxxxxxx>
Subject: [SI-LIST] Re: Voltage rating of a Ceramic capacitor
Date: Wed, 20 Jun 2001 13:05:11 -0400
I am very interested in why you recommended against the use of
Z5U or Y5V caps.
Thanks,
Mary Wilson
EMC Design Engineer
Astral Point Communications
(978) 367-6376
-----Original Message-----
From: HaroldLSJ@xxxxxxx [mailto:HaroldLSJ@xxxxxxx]
Sent: Wednesday, June 20, 2001 1:33 AM
To: si-list@xxxxxxxxxxxxx; ajmani@xxxxxxxxxx
Subject: [SI-LIST] Re: Voltage rating of a Ceramic capacitor
Ravinder,
I must correct the misinformation you have received concerning the voltage
rating of a ceramic capacitor and in particular for an X7R type dielectric.
First, ALL ceramic capacitors are tested to 2.5 times rated voltage so your
6.3V rating has been 100% tested to 15.75 volts. Further, the typical X7R
MLC (multilayer capacitor) will not breakdown until you reach a voltage
above
500V! The typical breakdown voltage I see is in the 500V to 800V range!
Second, the voltage coefficient for X7R caps at ten (10V) volts is less than
a negative 5% change in capacitance value and at five (5V) volts it is less
than a negative 2% change in capacitance so this will not be a problem.
Third, the typical temperature coefficient for X7R for this voltage range
will not change the capacitance value by more than a negative fifteen (15%)
percent from -55C to +125C and is most likely to be less than -10%.
Fourth, the biggest factor from a SI standpoint is the change in capacitance
value with frequency. This should be qualified on a part by part basis.
The
typical X7R will drop ten (10%) percent of its value from zero to 1MHz so
get
a good high frequency gain/phase meter and compare your tantalum and the X7R
you plan to use then adjust accordingly. If your frequency is extremely
high, consider using a porcelain microwave cap. An NPO cap has almost zero
capacitance drop across this same frequency span.
Remember an MLC is a miniature thick film hybrid circuit so test and mount
the cap with the plates normal (vertical) to the PCB trace.
Finally, ceramic caps like tantalums usually fail by shorting. If you
require high reliability, then request the lot be HALT (highly accelerated
life testing) qualified which is usually a maximum failure rate of between 5
to 8 caps out of 55 tested from the lot you are interested in buying. For
extreme high reliability (zero failures), have the caps 100% HALT sorted.
HALT testing will always find more failures than Mil testing. X7R will
always have a higher reliability than NPO and don't use Z5U or Y5V. There
is
not enough room here to discuss this further so email me direct if you need
more info on reliability.
Harold L. Snyder, Jr.
Scientist & Consultant
Begin Included Message:
==========================
> Subj: [SI-LIST] Voltage rating of a Ceramic capacitor
> Date: 6/14/2001 5:13:41 PM Central Daylight Time
> From: ajmani@xxxxxxxxxx (Ravinder Ajmani)
> Sender: si-list-bounce@xxxxxxxxxxxxx
> Reply-to: si-list@xxxxxxxxxxxxx
> To: si-list@xxxxxxxxxxxxx
>
>
>
> I have been asked to replace Tantalum bulk capacitor in a design with a
> suitable Ceramic capacitor. The Ceramic capacitor is X5R type, which I
> believe is more stable than Y5V. However, its voltage rating being 6.3V,
I
> am not feeling very comfortable to use it in the 5V application. Can
> anyone advise me about the minimum voltage rating I should have for a bulk
> Ceramic capacitor in a 5V application.
>
> Regards, Ravinder
> PCB Development and Design Department
> IBM Corporation
> Email: ajmani@xxxxxxxxxx
>
***************************************************************************
> Always do right. This will gratify some people and astonish the rest.
> .... Mark Twain
>
>
==========================
End Included Message.
------------------------------------------------------------------
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------------------------------
From: "Cruz, Jose" <Jose.Cruz@xxxxxxxxxx>
Subject: [SI-LIST] Re: Voltage rating of a Ceramic capacitor
Date: Wed, 20 Jun 2001 13:35:03 -0400
I would like to know why you have X7R better than NPO. I believe=20
the correct order is NPO, X7R, Z5U/Y5V. The NPO is the more=20
pure ceramic with low dielectric constant. X7R is the next one in=20
line. The additives used to get a higher dielectric constant will=20
deteriorate the electrical/mechanical characteristics. Some
applications can live with this.
X5R is basically the same as X7R. The X5R will have a capacitance
change of +/- 15% in a temperature range of -55=B0C to 85=B0C while X7R =
will have the same capacitance change but the temperature range is=20
-55=B0C to 125=B0C.
Jose
-----Original Message-----
From: Wilson, Mary [mailto:MWilson@xxxxxxxxxxxxxxx]
Sent: Wednesday, June 20, 2001 1:05 PM
To: 'si-list@xxxxxxxxxxxxx'
Subject: [SI-LIST] Re: Voltage rating of a Ceramic capacitor
I am very interested in why you recommended against the use of
Z5U or Y5V caps.=20
Thanks,
Mary Wilson
EMC Design Engineer
Astral Point Communications
(978) 367-6376
-----Original Message-----
From: HaroldLSJ@xxxxxxx [mailto:HaroldLSJ@xxxxxxx]
Sent: Wednesday, June 20, 2001 1:33 AM
To: si-list@xxxxxxxxxxxxx; ajmani@xxxxxxxxxx
Subject: [SI-LIST] Re: Voltage rating of a Ceramic capacitor
Ravinder,
I must correct the misinformation you have received concerning the =
voltage=20
rating of a ceramic capacitor and in particular for an X7R type =
dielectric.
First, ALL ceramic capacitors are tested to 2.5 times rated voltage so =
your=20
6.3V rating has been 100% tested to 15.75 volts. Further, the typical =
X7R=20
MLC (multilayer capacitor) will not breakdown until you reach a voltage
above=20
500V! The typical breakdown voltage I see is in the 500V to 800V =
range!
Second, the voltage coefficient for X7R caps at ten (10V) volts is less =
than
a negative 5% change in capacitance value and at five (5V) volts it is =
less=20
than a negative 2% change in capacitance so this will not be a problem.
Third, the typical temperature coefficient for X7R for this voltage =
range=20
will not change the capacitance value by more than a negative fifteen =
(15%)=20
percent from -55C to +125C and is most likely to be less than -10%.
Fourth, the biggest factor from a SI standpoint is the change in =
capacitance
value with frequency. This should be qualified on a part by part =
basis.
The=20
typical X7R will drop ten (10%) percent of its value from zero to 1MHz =
so
get=20
a good high frequency gain/phase meter and compare your tantalum and =
the X7R
you plan to use then adjust accordingly. If your frequency is =
extremely=20
high, consider using a porcelain microwave cap. An NPO cap has almost =
zero=20
capacitance drop across this same frequency span.
Remember an MLC is a miniature thick film hybrid circuit so test and =
mount=20
the cap with the plates normal (vertical) to the PCB trace.
Finally, ceramic caps like tantalums usually fail by shorting. If you=20
require high reliability, then request the lot be HALT (highly =
accelerated=20
life testing) qualified which is usually a maximum failure rate of =
between 5
to 8 caps out of 55 tested from the lot you are interested in buying. =
For=20
extreme high reliability (zero failures), have the caps 100% HALT =
sorted. =20
HALT testing will always find more failures than Mil testing. X7R will =
always have a higher reliability than NPO and don't use Z5U or Y5V. =
There
is=20
not enough room here to discuss this further so email me direct if you =
need=20
more info on reliability.
Harold L. Snyder, Jr.
Scientist & Consultant
Begin Included Message:
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D
> Subj: [SI-LIST] Voltage rating of a Ceramic capacitor
> Date: 6/14/2001 5:13:41 PM Central Daylight Time
> From: ajmani@xxxxxxxxxx (Ravinder Ajmani)
> Sender: si-list-bounce@xxxxxxxxxxxxx
> Reply-to: si-list@xxxxxxxxxxxxx
> To: si-list@xxxxxxxxxxxxx
>=20
>=20
>=20
> I have been asked to replace Tantalum bulk capacitor in a design with =
a
> suitable Ceramic capacitor. The Ceramic capacitor is X5R type, which =
I
> believe is more stable than Y5V. However, its voltage rating being =
6.3V,
I
> am not feeling very comfortable to use it in the 5V application. Can
> anyone advise me about the minimum voltage rating I should have for a =
bulk
> Ceramic capacitor in a 5V application.
>=20
> Regards, Ravinder
> PCB Development and Design Department
> IBM Corporation
> Email: ajmani@xxxxxxxxxx
>
************************************************************************=
***
> Always do right. This will gratify some people and astonish the =
rest.
> .... Mark Twain
>=20
>=20
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D
End Included Message.
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=20
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=20
------------------------------
Date: Wed, 20 Jun 2001 09:57:16 -0700
From: "S. Weir" <weirsp@xxxxxxxxxx>
Subject: [SI-LIST] Re: Crosstalk between different layers
Roberto,
That formula is the crosstalk limit for two adjacent microstrips. H is the
height from signal to the nearest reflection plane.
Four layer boards present a compromise between signal layer to plane
height, and spacing requirements to meet crosstalk. In most cases, you
will want to put the two planes in the middle, and keep them as close
together as possible. For a 31 mil stack up, and 3 mils plane to plane,
this will yield approximately 14 mils from signal to plane. So by the
formula, the worst case center to center spacing required would be about 50
mils. But this only applies for lines that are a significant portion of
the rise time. If you have really fast signals, consider going to six
layers or a faster board. If you move the planes away from each other, the
inductance rises quickly and you will be far more susceptible to
simultaneous switching noise.
Regards,
Steve.
At 03:46 PM 6/21/01 +0200, you wrote:
>Hi all,
>
>I'm investigating this configuration in order to estimate the crosstalk
>between L2 and L3.
>
>L1 ------------- Plane (GND)
>L2 --- signal
>L3 --- signal
>L4 ------------- Plane (Power)
>
>My target is to obtain a minimum spacing between the two layers that allow
>a maximum
>crosstalk level (for example < 5%).
>I'm wondering if I can use the H.Johnson book formula :
>
>crosstalk < 1/[1+(D/H)^2].
>
>If yes, assuming a ground-signal distance of 5 mils and a signal-signal
>distance of 20 mils,
>which is the value I have to use for H?
>
>And if one signal layer is 90 degree routed, there is any difference?
>
>In H.Johnson book section 5.8.5 (ten-layer stack) there is a similar
>configuration:
>the crosstalk between layers 4 and 6 is determined by the ratio of
>separation to ground plane
>height. But I don't understood how the geometric average height of 0.007
>inch is calculated.
>
>Thanks in advance.
>
>Roberto Carretta.
>
>
>
>------------------------------------------------------------------
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>
------------------------------
Subject: [SI-LIST] IBIS2XTK v. SPI2MOD
From: Adam.Tambone@xxxxxxxxxxxxxxxxx
Date: Wed, 20 Jun 2001 14:04:17 -0400
Hello SI Gurus,
Can anyone tell me if there any advantages of using XTK models generated by
IBIS2XTK v. SPI2MOD and vice-versa? Specifically I am interested in
differential models.
Thanks,
Adam Tambone
------------------------------
From: ABOUJEYAB@xxxxxxx
Date: Wed, 20 Jun 2001 15:01:03 EDT
Subject: [SI-LIST] Re: IBIS2XTK v. SPI2MOD
Hi Adam...
First of all, if an ibis model is available it's easier to generate xtk
files
from IBIS2XTK,
since you don't have to worry about producing spice output files to use with
SPI2MOD.
As far as accuracy, from my experience I found them to be very close.
Both IBIS2XTK and SPI2MOD do not like non-monotonicity in the VT curves
and will try to straighten this out. SPI2MOD doesn't like non-monotinicity
in
the VI curve, whereas IBIS2XTK doesn't like it in the following sums:
HIGH+SHUNT and LOW+SHUNT.
That's okay, because in one of my previous
simulations I compared the original spice simulation (which has non-
monotonicity) with xtk simulation (monotonicity is straightened) and
the results were very close. That means in real life monotonicity doesn't
affect
you very much because it will be reduced by introducing package capacitance
and all the inductances on the board.
Another thing that the XTK manual mentiones is that SPI2MOD is designed
to be used with enhanced models excluding the multi-VI devices. So if your
driver has two stages of pull-ups and pull-downs, or a more complex design
then
SPI2MOD as it is doesn't produce accurate models. You have to run separate
SPICE simulation for individual stages and becomes complicated, and I don't
know
how to do that.
In short, if you have ibis models and you trust them, then use them.
Also, I don't think there is any special treatment for differential models.
If somone or someones disagree with me that's okay, I'm still learning and
would appreciate any correction or addition to my assesment.
Thanks,.
Tariq Abou-Jeyab
------------------------------
Subject: [SI-LIST] Re: IBIS2XTK v. SPI2MOD
From: Adam.Tambone@xxxxxxxxxxxxxxxxx
Date: Wed, 20 Jun 2001 15:58:25 -0400
Tariq,
Thank you very much for your detailed response. I learned a great amount
from it. I have already generated the IBIS2XTK models and they are working
well but before you replied I wondered if it would be worth the effort of
generating the SPI2MOD models. I will probably go ahead and generate them
for the education, but it is very good to hear and learn from your
experiences. I certainly appreciate your reply.
Thank You Again,
Adam Tambone
ABOUJEYAB@xxxxxxx@freelists.org on 06/20/2001 03:01:03 PM
Please respond to si-list@xxxxxxxxxxxxx
Sent by: si-list-bounce@xxxxxxxxxxxxx
To: si-list@xxxxxxxxxxxxx
cc: ABOUJEYAB@xxxxxxx
Subject: [SI-LIST] Re: IBIS2XTK v. SPI2MOD
Hi Adam...
First of all, if an ibis model is available it's easier to generate xtk
files
from IBIS2XTK,
since you don't have to worry about producing spice output files to use
with
SPI2MOD.
As far as accuracy, from my experience I found them to be very close.
Both IBIS2XTK and SPI2MOD do not like non-monotonicity in the VT curves
and will try to straighten this out. SPI2MOD doesn't like non-monotinicity
in
the VI curve, whereas IBIS2XTK doesn't like it in the following sums:
HIGH+SHUNT and LOW+SHUNT.
That's okay, because in one of my previous
simulations I compared the original spice simulation (which has non-
monotonicity) with xtk simulation (monotonicity is straightened) and
the results were very close. That means in real life monotonicity doesn't
affect
you very much because it will be reduced by introducing package capacitance
and all the inductances on the board.
Another thing that the XTK manual mentiones is that SPI2MOD is designed
to be used with enhanced models excluding the multi-VI devices. So if your
driver has two stages of pull-ups and pull-downs, or a more complex design
then
SPI2MOD as it is doesn't produce accurate models. You have to run separate
SPICE simulation for individual stages and becomes complicated, and I don't
know
how to do that.
In short, if you have ibis models and you trust them, then use them.
Also, I don't think there is any special treatment for differential models.
If somone or someones disagree with me that's okay, I'm still learning and
would appreciate any correction or addition to my assesment.
Thanks,.
Tariq Abou-Jeyab
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------------------------------
From: "Peterson, James F (FL51)" <james.f.peterson@xxxxxxxxxxxxx>
Subject: [SI-LIST] copper thickness of a ref plane
Date: Wed, 20 Jun 2001 16:30:51 -0400
Because of physical limitations, I am considering reducing all of the ref
planes on a design to 1/2 oz. copper (was 1 oz. copper). The board level
logic is 3.3V CMOS. Does anybody see any problems with doing this?
thanks,
Jim
------------------------------
From: "Greim, Michael" <mgreim@xxxxxxxxxxxx>
Subject: [SI-LIST] Re: copper thickness of a ref plane
Date: Wed, 20 Jun 2001 16:59:22 -0400
Make sure that the ampacity of a half ounce plane
is adequate for your needs. What is driving your
decision to head in this direction? There may be
a better alternative.
Best Regards,
Michael C. Greim Sonus Networks
mgreim@xxxxxxxxxxxx 978-589-8336
Making the world safe for digital signals everywhere
And all this science I don't understand
It's just my job six days a week
The time is gone. The email's over
Thought I'd something more to say......
-----Original Message-----
From: Peterson, James F (FL51) [mailto:james.f.peterson@xxxxxxxxxxxxx]
Sent: Wednesday, June 20, 2001 4:31 PM
To: si-list@xxxxxxxxxxxxx
Subject: [SI-LIST] copper thickness of a ref plane
Because of physical limitations, I am considering reducing all of the ref
planes on a design to 1/2 oz. copper (was 1 oz. copper). The board level
logic is 3.3V CMOS. Does anybody see any problems with doing this?
thanks,
Jim
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------------------------------
From: "Sweetman, Eric (Eric)" <esweetman@xxxxxxxxxx>
Subject: [SI-LIST] Re: Hspice core dump
Date: Wed, 20 Jun 2001 17:10:46 -0400
Regarding David's comment,
One thing I've found that will freeze an HSPICE simulation faster than
liquid nitrogen is to run the simulation under any PATH whose directories or
filenames include spaces -- perfectly legal under WIn95 and later but not OK
with HSPICE which carries it's UNIX heritage with it in varied and confusing
ways.
For example:
D:\simulations\HSpice\projectA\testrun.sp is OK
D:\My Simulations\HSpice\projectA\testrun.sp is NOT!
Eric Sweetman
------ ORIGINAL MESSAGE FROM David Haedge <haedge@xxxxxxxxxxxx> -------
Date: Mon, 18 Jun 2001 14:09:41 -0500
From: David Haedge <haedge@xxxxxxxxxxxx>
Subject: [SI-LIST] Re: Hspice core dump
SIers,
I have experienced similar problems in the past with the
^M phenomenon in HSPICE. On occasion, HSPICE would
just stay in a perpetual funk. No error messages, no output,
no notification of progress finding a solution, just complete
non-response. I always had to kill the process to get
HSPICE to exit. I always traced the problem to a DOS formatted
model file trying to be read into the main HSPICE deck.
I had to "dos2unix' every model file being read and now do this
as a matter of course before running any newly acquired model
files. It only takes one ^M to shut everything down.
David Haedge
Raytheon
Eric Sweetman
Mailing address: Shipping address:
Lucent Technologies Bell Labs Rm. 2-3017
PO Box 900 Lucent Technologies Bell
Labs
Princeton, NJ 08542-0900 569 Carter Road
Hopewell, NJ
08525
Phone: (609)639-2447
FAX: (609)639-2447
esweetman@xxxxxxxxxx
------------------------------
Date: Wed, 20 Jun 2001 17:06:44 -0400
From: "Perry Qu" <perry.qu@xxxxxxxxxxx>
Subject: [SI-LIST] Re: copper thickness of a ref plane
James:
THe thickness of the plane is mainly determined by the power consumption of
your
card. I guess it's a similar idea as to how much current a wire can carry
with
certain diameter. However, we do use 0.5 oz copper all the time and no
problems
at all.
Regards
Perry
"Peterson, James F (FL51)" wrote:
> Because of physical limitations, I am considering reducing all of the ref
> planes on a design to 1/2 oz. copper (was 1 oz. copper). The board level
> logic is 3.3V CMOS. Does anybody see any problems with doing this?
>
> thanks,
> Jim
> ------------------------------------------------------------------
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------------------------------
Date: Wed, 20 Jun 2001 14:13:41 -0700
From: Mark Nass <markn@xxxxxxxxxxxxxxx>
Subject: [SI-LIST] Re: Validation of XTK results for clock skews
You can look in the ".TLP" file and see what impedance & speed you are
getting
for the 2 clock traces. Make sure they match your board, if they do not
check
all of the various parameters and stack up info in the ".gcf" file.
Are you using the ".tlp" file, check your ".xns" file and make sure you
have the statement FILES XLINE_PARAMETERS filename.tlp, otherwise you are
probably defaulting to the impedance and flightime specified with a
PARAMETER statement.
The way I like to line up the clocks is to simulate them one at a time and
then copy and paste the waveforms on top of each other. This allows me to
see the waveform and line up the clocks. You can also save the file in xy
format(.dat file) and read it into an Excel spreadsheet and create a graph
there. That way you can read in the measured waveform and have it in a
format
that does not require XTK to view the results.
Mark
At 09:13 AM 6/19/01 +0500, you wrote:
>
>
>
>
>Hello all,
>
>This question is related to validation of clock skews from XTK with
practical
>clock skews measured on board.
>I am interested in the clock skew between the CPU_CLOCK and the
CHIPSET_CLOCK.
>Practically, the skew has been measured on the CRO at the destination of
the
>CPU_CLOCK pin and the CHIPSET_CLOCK pin.
>>From XTK, I have measured the flight time for the CPU_CLOCK (i.e the
delay from
>the clock syntheziser pin to the CPU_CLOCK pin), and the flight time for
the
>CHIPSET_CLOCK (i.e, the delay from the clock synthesizer pin to the
>CHIPSET_CLOCK pin).
>I have calculated the clock skew to be the difference between the
>Tflight(CPU_CLOCK) and the Tflight(CHIPSET_CLOCK).
>The flight times have been calculated using the typical corner. The
simulated
>clock skew is nowhere close to the practical skews measured. The simulated
clock
>skews are from the board file. The skews have also been calculated for the
fast
>and slow corners.
>
>I would like to know,
>a) What are the parameters i need to take into for calculating the
simulated
>clock skews from XTK?
>b) Why is there a large difference between simulated and practical results?
>c) How do i measure the clock skew from XTK?
>d) Is the procedure i have followed for calculating the clock skew from XTK
>correct?
>
>Looking forward to your valued suggestions and help.
>
>
>Thanks and Regards,
>Suchitha
>
>
>
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>
>
>
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