[SI-LIST] Re: signal quality on unbuffered DIMM

Hello Sai,
Did you simulate the interface accross intended DIMM configurations and 
driver/rcvr strengths?  Loading differences are big between UDIMM and RDIMM and 
within the UDIMM the raw card loading for address/command can be between 4 and 
18 for a single slot. 
-Jory


----- Original Message ----
From: Jai Shanker <jswarrier@xxxxxxxxx>
To: si-list@xxxxxxxxxxxxx
Sent: Wednesday, July 30, 2008 7:07:18 PM
Subject: [SI-LIST] Re: signal quality on unbuffered DIMM


Hello all,

A while ago we designed a board targeting DDR2 unbuffered DIMM at 400MHz, 
800MT/s and faced significant problems with signal quality on the shared 
address/ control lines at the devices in the DIMM. An SI check had been done by 
the chip package provider, but fairly decoupled from us the board designers and 
some load issues missed.

We were able to fix it with registered DIMMs but havent ever been satisfied 
with "why the signals improved".

The register specd pretty much the same drive characteristics as our chip (in 
fact at full strength our chip drove better). Slew rates were comparable. DIMMs 
had the same organization and memories were the same.

The only real difference was 4" of PCB trace from the controller to the DIMM 
inputs + connector loading. But they were well designed, tighter than Micron 
technotes, had good signal quality at the DIMM pins.

What did we miss? Are registered DIMMs internal layouts a lot better than 
unbuffered ( in terms of balanced tree etc.) Any tips or shared experiences 
welcome.

Thanks,
Sai C
CPDevices


      
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