[SI-LIST] Re: s parameters and transient simulation
- From: Geoff Stokes <gstokes@xxxxxxxxx>
- To: "'dsmith@xxxxxxx'" <dsmith@xxxxxxx>,"'si-list@xxxxxxxxxxxxx'" <si-list@xxxxxxxxxxxxx>
- Date: Fri, 12 Dec 2003 12:40:42 -0000
Many thanks, Steve, Dave and Ege
There seems to be some agreement, at least, on the theory and the difficulty
of presentation. I have made enquiries with two major vendors but not found
any offer of a good solution. Some points on package modelling:
1. One of the papers by Steer's team at NCSU explains the idea of local
reference nodes for simulation of a microwave circuit. I suggest this has
immediate applications for SI and IC package modelling because it addresses
the problem of a distributed microwave or RF network, such as a package or a
connector, together with organising the connection nodes for interface to an
integrated circuit simulator.
The NCSU team are working on fREEDA:
http://guppie.egrc.ncsu.edu/freeda/
Also, Leeds Univ in UK is developing a unified approach, led by Christopher
Snowden.
However the *full solution* for a distributed packaged IC from DC to THz is
not yet commercially available and is unlikely to be so for at least a
couple of years.
2. The package alone can be accurately modelled using a fullwave 3D tool
such as Ansoft HFSS or CST Microwave Studio (which is my own choice so far).
Both have travelling wave ports and discrete nodal ports. The travelling
wave ports seem to be unsuitable for a structure with several terminals, as
there is a requirement for them to be well separated for accuracy.
3. The discrete ports have limited accuracy because of their finite size.
However, they can be made to work if carefully set up. Each port has its
own separate signal and return terminal. MWS has Discrete Ports and HFSS
has Gap Ports.
4. Because of the lack of the *full solution* of a 3D non-linear full-wave
simulator incorporating characterised semiconductor behaviour, we have to
divide the system into two parts. The first half is the chip, simulated in
Spice or similar using a nodal schematic picture, which is fundamentally
flawed of course, because wave couplings are not accurately represented,
even if transmission lines are used for the interconnects. However, the
chip is small enough that we can live with the errors, and we have no
choice. An important point is that the schematic has a single common ground
terminal to which all power and signal voltages are referred - this is part
of the lie. The second half is the package and local PCB interconnects,
represented as accurately as we can in a 3D EM simulator.
5. The EM simulator produces a file of s parameters. This is defined for n
ports. In the 3D model, these n ports had 2n terminals but this information
is not implicitly carried along with the s-parameter file.
6. We now leave the EM simulator behind and consider the circuit simulator.
How can these s-parameters be used with the chip circuit? This is where
Steer's local reference node idea comes in. These can be used in the n-port
element within the Cadence circuit simulator, together with the circuit
simulation of the chip. I must say I don't have a taste for modified nodal
admittance matrices, and economic pressures prevent their detailed
consideration. But perhaps we can gain some insight, remembering we need to
concentrate on true-as-possible representations of currents and differential
voltages. Dave's simple example of a microstrip with a gap port might help
the understanding here.
7. There is another difficulty, which Ege Engin has just pointed out. The
PCB side of the package has ports referred to the PCB ground plane - I see
no problem in joining those reference terminals together in the circuit
simulator. That is what we normally do when we consider a network of
transmission lines with spatially separated ports on a common ground
conductor. But the IC interface of the package has a number of bond pad
terminals quite close together. The ports of the package model would most
likely be referred to a common paddle connection, but this may not always be
possible. If there is a paddle connecting the IC substrate it works like a
local common ground plane, partly screening the IC from wave interaction
between its terminals and with the rest of the package. If this
approximation is valid, we can then join the IC reference terminals together
to form a single "local reference node", representing the paddle connection.
8. If we have faith in the validity of the s-parameters, and because the IC
ports and their local reference node have no interaction with the PCB side,
we can now join the paddle connection to common ground. It remains to be
added that the s-parameters must be valid from DC to RF, so that the total
effects of DC resistance, internal inductance, RF resistance and all AC and
wave couplings are included. This may require stitching s-parameter results
together from different frequency band runs in the EM simulator.
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