[SI-LIST] Re: risetime effects of plane breaks
- From: "Ken Cantrell" <Ken.Cantrell@xxxxxxxxxxxxxxxx>
- To: <weirsp@xxxxxxxxxx>, <Chris.Cheng@xxxxxxxxxxxx>
- Date: Mon, 24 Jan 2005 08:57:12 -0700
Steve,
Can you elaborate on what you mean by "For single-ended signals with the
"right"
configuration we can kill monotonicity". What type of monotonic behaviour
are you referring to?
And the same please for "For signal risetimes long compared to the signal
pitch, the effect is of
push-out / pull-in." Under what circumstances do you see push-out, and when
do you see pull-in?
And lastly, are there any practical cases where the rise-time is short
compared to the pitch? 50 mils is a
pretty wide pitch for a diff pair, and that would put your rise-time in the
tens of picoseconds, wouldn't it?
Thanks,
Ken
-----Original Message-----
From: si-list-bounce@xxxxxxxxxxxxx
[mailto:si-list-bounce@xxxxxxxxxxxxx]On Behalf Of steve weir
Sent: Thursday, January 20, 2005 9:22 PM
To: Chris.Cheng@xxxxxxxxxxxx
Cc: Si-List
Subject: [SI-LIST] Re: risetime effects of plane breaks
Chris, both, but mostly the solid ground plane behind the split.
The devil with diffs is as you guessed, we could push the signal right out
of the common mode range. For single-ended signals with the "right"
configuration we can kill monotonicity. For signal risetimes long compared
to the signal pitch, the effect is of push-out / pull-in. For rise-times
that are short compared to the pitch, the effect is more of a comb. The
test cases were 5H pitch. There are even more fun things that happen
depending on the size of the various features.
Best Regards,
Steve
At 06:54 PM 1/20/2005 -0800, Chris Cheng wrote:
>When you talk about displacement return, do you mean the solid ground plane
>on the opposite side of the stripline ? Or a plane on the opposite side of
>the split plane (like Doug's second experiment) ?
>Anyways, this may even have more serious implications on common mode noise
>on those Gb differential signals.
>
>-----Original Message-----
>From: steve weir [mailto:weirsp@xxxxxxxxxx]
>Sent: Thursday, January 20, 2005 6:41 PM
>To: Chris.Cheng@xxxxxxxxxxxx
>Cc: Si-List
>Subject: Re: [SI-LIST] Re: risetime effects of plane breaks
>
>
>Chris, well that is why we run the models to find out. I had believed
>similarly to you that with a solid ground plane behind the split that the
>current would mostly displace between the split and solid plane and we
>would not see a linear increase in noise with conductors. However, when
>Scott ran the models, he found a nearly linear increase. That means that
>most of the return current "across" the split is actually going around it
>via the split plane, and not forward across through displacement currents.
>
>Best Regards,
>
>
>Steve
>
>At 05:55 PM 1/20/2005 -0800, Chris Cheng wrote:
> >I am not sure about that. As the seperation between the traces increases,
> >the current loop area increases and so does the plane capacitance between
> >the power planes and the solid ground plane below. I am under the
>impression
> >that the current return through those plane capacitance. The same way
when
> >you run a stripline sandwiched between a power and ground plane where the
> >power plane has nothing to do with your IO power.
> >
> >-----Original Message-----
> >From: steve weir [mailto:weirsp@xxxxxxxxxx]
> >Sent: Thursday, January 20, 2005 5:50 PM
> >To: Chris.Cheng@xxxxxxxxxxxx
> >Cc: Si-List
> >Subject: Re: [SI-LIST] Re: risetime effects of plane breaks
> >
> >
> >Chris, emphasis that is worth repeating is the bus behavior doesn't
really
> >depend much on the width of the moat, and no practical number of bypass
> >capacitors will take care of edges at today's edge rates. We get
coupling
> >not only line to line over the moat, but the sum of return current that
now
> >circulates around the moat as we lose the TEM mode. I haven't seen the
> >model output, but I suspect that a victim at the outside of the bus
suffers
> >more than a victim at the center.
> >
> >Best Regards,
> >
> >
> >Steve
> >At 04:14 PM 1/20/2005 -0800, Chris Cheng wrote:
> > >Scott,
> > >Excellent summary. That was my concern on striplines crossing with a
bus
> > >rather than individual signals. In a way, it is like wire bond signal
>leads
> > >without the ground leads mixed among them. The signals start
referencing
> > >each other instead. Or you can see it as a trade-off between adding
> > >shielding layers or spreading the bus spacing (decreasing routing
>channels)
> > >in a high density/performance design. My own rule of thumb is space
them
>at
> > >least equal or larger than the gap itself when crossing. That's is at
>least
> > >a 3x decrease in routing channels so it is quite costly and has to be
> >weight
> > >against adding shielding layers. Sometimes its worth it, sometimes its
>not.
> > >As for EMI, if you dig back some discussion I had with Steve, I always
> > >prefer solid ground planes referencing microstrips on top and bottom of
>PCB
> > >and then stitch the edges with ground vias. Hopefully any of those
>excited
> > >noise on the cut power planes will be trapped inside.
> > >
> > >-----Original Message-----
> > >From: Scott McMorrow [mailto:scott@xxxxxxxxxxxxx]
> > >Sent: Thursday, January 20, 2005 2:39 PM
> > >Cc: Si-List
> > >Subject: [SI-LIST] Re: risetime effects of plane breaks
> > >
> > >
> > >When this thread started I was on vacation. However, I found this
> > >interesting enough to resurrect some previous simulations I'd performed
> > >in CST Microwave Studio. After much playing, twiddling and generally
> > >having fun I can say several things:
> > >1) It's pretty easy to confirm Doug's results using 3D fullwave
> > >simulation. In fact, in about 30 minutes I can replicate his case and
> > >create a design that can be easily modified for many other
> > >possibilites. The microstrip split plane crossing is a no-brainer.
> > >Just don't do it and expect anything approaching an EMI "clean" system.
> > >
> > >2) Chris and Steve ... and eventually myself, wanted to know more about
> > >the various different stripline plane crossing configurations, so I
> > >setup a simulation with a VDD island not unlike what might be found in
a
> > >memory system, and performed multiple simulations with dual asymmeteric
> > >stripline crossing the plane twice on it's way to the memory module.
Not
> > >surprisingly the following is true:
> > >
> > > It is best not to cross a split plane ... even with stripline.
> > > If you do, it is better to cross a split that is adjacent to a
> > > ground plane
> > > It is even better if you cross a split adjacent to a ground plane
on
> > > the stripline layer furthest away from the split plane (i.e. next
to
> > > a ground plane)
> > > It is worst to cross a split plane that has no adjacent ground.
> > > The width of the gap in the plane makes very little difference
until
> > > it becomes really small or really big.
> > > Crosstalk scales almost linearly with the number of aggressors
> > > crossing the split. (i.e. - it can get really bad!)
> > > Bypass of the split power island helps for frequencies below 500
> > > MHz, provides no help for frequencies higher than 500 MHz, and as
> > > such has no benefit to most of the noise and crosstalk created by
> > > high speed signals crossing onto and off of the island.
> > >
> > >The energy released into the power/ground plane cavities by high speed
> > >signal split plane crossings is huge and essentially cannot be
> > >suppressed with bypass capacitors. Any attempt at supprerssion with
> > >capacitors exhibits what I call a "Whack-A-Mole" property. You can
> > >never get rid of those pesky little moles. All you can do is to move
> > >them around by thumping them. Given that all this energy is rattling
> > >around the PCB power planes from split plane crossings, it will
> > >eventually go somewhere. Since it's really easy to develop all sorts
of
> > >resonant power island cavities that have primary resonant frequencies
in
> > >the 500 MHz to several GHz range, it is not at all unlikely that any
> > >split plane crossing has an extremely strong potential to excite a
> > >resonance in a frequency range that will cause most systems to fail EMC
> > >compliance testing About all you can do is to shield the cavity
patches
> > >using ground layers. This should reduce the radiated energy
> > >significantly, but will not totally eliminate it, since eventually it
> > >will find it's way to all those pesky device and package leads.
> > >
> > >
> > >best regards,
> > >
> > >Scott
> > >
> > >--
> > >Scott McMorrow
> > >Teraspeed Consulting Group LLC
> > >121 North River Drive
> > >Narragansett, RI 02882
> > >(401) 284-1827 Business
> > >(401) 284-1840 Fax
> > >
> > >http://www.teraspeed.com
> > >
> > >Teraspeed is the registered service mark of
> > >Teraspeed Consulting Group LLC
> > >
> > >
> > >
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