[SI-LIST] Re: risetime effects of plane breaks
- From: "Brad Crowell" <brad.crowell@xxxxxxxxxx>
- To: <weirsp@xxxxxxxxxx>, "Si-List" <si-list@xxxxxxxxxxxxx>
- Date: Fri, 21 Jan 2005 09:22:30 -0400
Yes, that is what I am suggesting. This would probably be a closer analogy
to a board to board connector than IC bond wires, as the physical scale
would be closer to the connector situation.
Brad
> -----Original Message-----
> From: si-list-bounce@xxxxxxxxxxxxx
> [mailto:si-list-bounce@xxxxxxxxxxxxx]On Behalf Of steve weir
> Sent: January 21, 2005 9:06 AM
> To: brad.crowell@xxxxxxxxxx; Si-List
> Subject: [SI-LIST] Re: risetime effects of plane breaks
>
>
> Brad, are you proposing parallel tracks on the signal layer
> interdigitated
> 1:N signal traces that extend completely across an island?
>
> Steve
> At 08:50 AM 1/21/2005 -0400, Brad Crowell wrote:
> >Chris's analogy to wire bonding makes me wonder if this would be
> helpful in
> >crossing splits. Assuming one can't avoid it and has to cross a
> plane split
> >with a bus, would including several traces from one part of the
> >plane, across the split, to another area of the plane be helpful
> in reducing
> >the negative effects of the split? In theory, this would provide a
> >continuous path for the return currents on that plane that is
> more closely
> >coupled to the signals than would otherwise result. This should
> then provide
> >some benefit.
> >
> >Brad
> >****************************
> >Brad Crowell, P. Eng.
> >Senior Hardware Designer
> >AMIRIX Systems
> >Phone: 902-450-1700 Ext 287
> >Fax: 902-450-1704
> >www.amirix.com
> >****************************
> > > -----Original Message-----
> > > From: si-list-bounce@xxxxxxxxxxxxx
> > > [mailto:si-list-bounce@xxxxxxxxxxxxx]On Behalf Of Chris Cheng
> > > Sent: January 20, 2005 8:14 PM
> > > Cc: Si-List
> > > Subject: [SI-LIST] Re: risetime effects of plane breaks
> > >
> > >
> > > Scott,
> > > Excellent summary. That was my concern on striplines crossing
> with a bus
> > > rather than individual signals. In a way, it is like wire bond
> > > signal leads
> > > without the ground leads mixed among them. The signals start
> referencing
> > > each other instead. Or you can see it as a trade-off between adding
> > > shielding layers or spreading the bus spacing (decreasing routing
> > > channels)
> > > in a high density/performance design. My own rule of thumb is
> > > space them at
> > > least equal or larger than the gap itself when crossing. That's
> > > is at least
> > > a 3x decrease in routing channels so it is quite costly and has
> > > to be weight
> > > against adding shielding layers. Sometimes its worth it,
> > > sometimes its not.
> > > As for EMI, if you dig back some discussion I had with Steve, I always
> > > prefer solid ground planes referencing microstrips on top and
> > > bottom of PCB
> > > and then stitch the edges with ground vias. Hopefully any of
> those excited
> > > noise on the cut power planes will be trapped inside.
> > >
> > > -----Original Message-----
> > > From: Scott McMorrow [mailto:scott@xxxxxxxxxxxxx]
> > > Sent: Thursday, January 20, 2005 2:39 PM
> > > Cc: Si-List
> > > Subject: [SI-LIST] Re: risetime effects of plane breaks
> > >
> > >
> > > When this thread started I was on vacation. However, I found this
> > > interesting enough to resurrect some previous simulations I'd
> performed
> > > in CST Microwave Studio. After much playing, twiddling and generally
> > > having fun I can say several things:
> > > 1) It's pretty easy to confirm Doug's results using 3D fullwave
> > > simulation. In fact, in about 30 minutes I can replicate his case and
> > > create a design that can be easily modified for many other
> > > possibilites. The microstrip split plane crossing is a no-brainer.
> > > Just don't do it and expect anything approaching an EMI
> "clean" system.
> > >
> > > 2) Chris and Steve ... and eventually myself, wanted to know
> more about
> > > the various different stripline plane crossing configurations, so I
> > > setup a simulation with a VDD island not unlike what might be
> found in a
> > > memory system, and performed multiple simulations with dual
> asymmeteric
> > > stripline crossing the plane twice on it's way to the memory
> module. Not
> > > surprisingly the following is true:
> > >
> > > It is best not to cross a split plane ... even with stripline.
> > > If you do, it is better to cross a split that is adjacent to a
> > > ground plane
> > > It is even better if you cross a split adjacent to a
> ground plane on
> > > the stripline layer furthest away from the split plane
> (i.e. next to
> > > a ground plane)
> > > It is worst to cross a split plane that has no adjacent ground.
> > > The width of the gap in the plane makes very little
> difference until
> > > it becomes really small or really big.
> > > Crosstalk scales almost linearly with the number of aggressors
> > > crossing the split. (i.e. - it can get really bad!)
> > > Bypass of the split power island helps for frequencies below 500
> > > MHz, provides no help for frequencies higher than 500 MHz, and as
> > > such has no benefit to most of the noise and crosstalk created by
> > > high speed signals crossing onto and off of the island.
> > >
> > > The energy released into the power/ground plane cavities by high speed
> > > signal split plane crossings is huge and essentially cannot be
> > > suppressed with bypass capacitors. Any attempt at supprerssion with
> > > capacitors exhibits what I call a "Whack-A-Mole" property. You can
> > > never get rid of those pesky little moles. All you can do is to move
> > > them around by thumping them. Given that all this energy is rattling
> > > around the PCB power planes from split plane crossings, it will
> > > eventually go somewhere. Since it's really easy to develop
> all sorts of
> > > resonant power island cavities that have primary resonant
> frequencies in
> > > the 500 MHz to several GHz range, it is not at all unlikely that any
> > > split plane crossing has an extremely strong potential to excite a
> > > resonance in a frequency range that will cause most systems
> to fail EMC
> > > compliance testing About all you can do is to shield the
> cavity patches
> > > using ground layers. This should reduce the radiated energy
> > > significantly, but will not totally eliminate it, since eventually it
> > > will find it's way to all those pesky device and package leads.
> > >
> > >
> > > best regards,
> > >
> > > Scott
> > >
> > > --
> > > Scott McMorrow
> > > Teraspeed Consulting Group LLC
> > > 121 North River Drive
> > > Narragansett, RI 02882
> > > (401) 284-1827 Business
> > > (401) 284-1840 Fax
> > >
> > > http://www.teraspeed.com
> > >
> > > Teraspeed is the registered service mark of
> > > Teraspeed Consulting Group LLC
> > >
> > >
> > >
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