[SI-LIST] Re: risetime effects of plane breaks
- From: steve weir <weirsp@xxxxxxxxxx>
- To: Chris.Cheng@xxxxxxxxxxxx
- Date: Tue, 18 Jan 2005 13:15:37 -0800
Chris, a microstrip will tend to be more EMC trouble, but it can be done,
and certainly has many times, particularly if one reserves the board edges
for ground fill. Depending on the type of parts and density opportunity
for traces on the component side could be quite limited. As far as ground
on the top, more rather than less properly stitched ground fill is almost
always a good thing.
W/o that extra shield provided by the box, stripline is proven to make EMC
compliance easier. You can go all the way back to papers in the early
1980's to see comparisons. It doesn't mean that you can't you microstrip
and an argument can be made that given a choice of remaining microstrip for
100% of the route versus exciting the cavities, an end to end microstrip
can actually sometimes be better both SI and EMC-wise. As with most
issues, it depends on the circumstances.
Best Regards,
Steve
At 12:07 PM 1/18/2005 -0800, Chris Cheng wrote:
>Steve, John and Doug,
>I have to say this is more on consumer/high volume cost sensitive EMI gig
>which I have no experience in. But why is signal on top of solid gnd type
>microstrip so evil that you have to start off with com/gnd fill or gnd/power
>fill on top and bottom layers ? At 50-60MHz, microstrip should be more than
>enough for SI. Hack I can make a case it will be great to route PECL
>highspeed differential signals on top straight from component to component
>without vias. Does stripline buys you that much EMI margin in low end boxes
>? Speaking for racks like server or even workstations design, they harder
>matter. Crossing cut planes with single ended microstrip signals is obvious
>bad.
>
>-----Original Message-----
>From: steve weir [mailto:weirsp@xxxxxxxxxx]
>Sent: Monday, January 17, 2005 8:45 AM
>To: John Matthews; Chris.Cheng@xxxxxxxxxxxx
>Cc: 'SI-List'
>Subject: RE: [SI-LIST] Re: risetime effects of plane breaks
>
>
>John, don't you have a problem with warpage
>
>There are a couple of things to consider here:
>
>1. A cavity may be broken-up with either an open or a short.
>a. Use ferrites and bypass caps to break-up voltage planes.
>b. Use stitching vias to break-up ground / ground cavities
>
>2. Your present layout does ugly things when signals switch from layer 2 to
>layer 3.
>
>3. If you are running high edge rate signals on layer 2 across splits in
>layer 1, you are creating problems.
>
>I would suggest you look hard at the feasibility of:
>
>1. Comp / gnd fill
>thick dielectric
>2. S E/W routes
>thin dielectric
>3 Gnd / 3v3 E/W stripes
>core dielectric
>4. Gnd / 3v3 N/S stripes
>thin dielectric
>5. S N/S routes
>thick
>6. 1V8 / gnd fill
>
>Depending on how much 3v3 power you need and where, this may or may not
>work for you. Any given stripe would be as wide as practical and stitched
>frequently to the matching polarity stripes on the adjacent layer. Fast
>edge rate signals would track only over the ground stripes. Spacing from
>1-2 would be substantially greater than from 2-3, ditto for 5-6 vs 4-5.
>
>Now, the vias effect small cavities for both the GND and 3v3 layers. You
>have some additional flexibility on whether to forego the ferrites to
>divide the 3v3 islands or not. They still form cavities with layer 1 and
>layer 6 fill, so if you can afford the limitation in signal returns, you
>can gain with the ferrites. However, if you cannot, emphasizing ground
>perimeter on 1 and 6 and stitching that through to an outer perimeter of
>gnd on 3 and 4 should work pretty well. You can think of this scheme as
>essentially a differential routing method.
>
>The main disadvantage of this method is the inductance that you will see
>between the 3v3 and ground. However, since you have adopted an islanding
>approach, you are already largely at the mercy of your bypass caps. If you
>are clever with your sizing and placement, you can mitigate the difference
>between this approach and what you have been doing.
>
>Steve.
>
>
>
>
>At 04:35 PM 1/17/2005 +0000, John Matthews wrote:
> >I find this discussion very interesting because of the method we used to
> >reduce EMI on our boards.
> >
> >We do router boards with various telecoms interfaces. They operate off a
> >wallplug 5V power supply,
> >and are shipped in a plastic case. The boards are six layer, from top to
> >bottom as follows:
> >
> >1. Components and ground fill
> >2. Signal
> >3. Signal
> >4. Ground
> >5. 3V3
> >6. 1V8 and ground fill
> >
> >The ground fills are stitched at 15mm intervals.
> >
> >Over the last year we've migrated to this from our initial efforts,
> >which were classical
> >sig-sig-pwr-gnd-sig-sig
> >
> >In relation to the experiments with split planes, we have found that the
> >only way to reduce EMI on our boards has been to
> >break up the 3V3 and 1V8 planes into smaller planes.
> >
> >Initially we had huge problems with radiated EMC at approx 500MHz
> >upwards. Main bus clock was between 50-66MHz.
> >Board size was approx 220x150mm, the planes were not entirely
> >rectangular, but the longest diagonal was 260mm.
> >
> >We took the approach of breaking up the power planes into more localised
> >planes connected to the source with ferrites.
> >As our planes have got smaller, we've seen the EMC frequencies increase,
> >so our main problem is now at 850MHz.
> >
> >Unfortunately this corresponds with one of the ground plane diagonals
> >(176mm) and we are concluding that this is one of the
> >resonant frequencies of the plane.
> >
> >I'm a bit stuck for ideas now, because my one golden rule is not to
> >split the ground plane. But that's my problem.
> >
> >I'm interested, because the experiments discussed suggest that split
> >planes will cause you problems, in our case we've
> >found that we had to do this, because it was the planes themselves were
> >radiating. Are we simply dealing with the lesser of
> >two evils in my case?
> >
> >
> >-----Original Message-----
> >From: si-list-bounce@xxxxxxxxxxxxx [mailto:si-list-bounce@xxxxxxxxxxxxx]
> >On Behalf Of steve weir
> >Sent: 15 January 2005 00:03
> >To: Chris.Cheng@xxxxxxxxxxxx
> >Cc: SI-List
> >Subject: [SI-LIST] Re: risetime effects of plane breaks
> >
> >
> >Chris, wire, insulator, plane w/split, dielectric, solid plane.
> >
> >Best Regards,
> >
> >
> >Steve.
> >
> >At 03:35 PM 1/14/2005 -0800, Chris Cheng wrote:
> > >Doug,
> > >Just try to understand your new stack up,
> > >is it :
> > >signal-splitplane-solid plane
> > >or
> > >splitplane-signal-solid plane ?
> > >
> > >-----Original Message-----
> > >From: Doug Smith [mailto:doug@xxxxxxxxxx]
> > >Sent: Friday, January 14, 2005 3:17 PM
> > >To: weirsp@xxxxxxxxxx
> > >Cc: emcesd2000@xxxxxxxxx; SI-List
> > >Subject: [SI-LIST] Re: risetime effects of plane breaks
> > >
> > >
> > >Wow! I didn't realize my little article would stimulate so many
> > >postings. Having a good discussion like this is good for us all.
> > >
> > >While teaching a seminar in San Diego yesterday I did a slight
> > >modification of the split plane board I used for my article this month.
> >
> > >I covered the bottom plane split (opposite signal wire with copper tape
> >
> > >and measured the ESD immunity via radiation from an ESD event. This was
> >
> > >the first time for this setup and live for the class. I scoured the
> > >tape many times to make sure connection was made through the
> > >"conductive" adhesive.
> > >
> > >The immunity was significantly worst (0.5 Volts induced in path) than
> > >the path over solid plane (0.1 Volt) and better than the path where
> > >both planes were cut (1.5 Volts induced EMI).
> > >
> > >Doug
> > >
> > >For the 30 or so mil plane spacing of the board
> > >
> > >steve weir wrote:
> > > > Oscar, yes, it is quite a dramatic effect isn't it? I suspect that
> >
> > > > when Lee says "it depends on how you do it" he has another
> > > > contiguous plane, ie
> > >
> > > > ground underneath the split as opposed to a split on all planes as
> > > > in Doug's experiment. Assuming lots of decoupling between each of
> > > > the
> > >islands
> > > > and the common ground plane the jump in coupling between lines
> > > > would be greatly suppressed.
> > > >
> > > > Regards,
> > > >
> > > >
> > > > Steve.
> > > >
> > > > At 11:00 AM 1/10/2005 -0800, Ahmad Fallah wrote:
> > > >
> > > >>Hi Steve,
> > > >>
> > > >>I have repeated Doug's experiment with a modified fixture where an
> > > >>additional trace (victim) was added near (~1 cm) the "signal" line
> > > >>for X-talk measurements. I have measured a 10-fold increase in
> > > >>x-talk amplitude in going from Case 1 to Case 2.
> > > >>
> > > >>Case 1: the offending and victim lines are both drawn over a solid
> > > >>return plane. Case 2: the offending and victim lines are both drawn
> > > >>over the cut in the return plane
> > > >>
> > > >>Regards,
> > > >>
> > > >>Oscar
> > > >>
> > > >>
> > > >>
> > > >>steve weir <weirsp@xxxxxxxxxx> wrote:
> > > >>
> > > >>Lee, the 5cm is the length of the break. The break is only about
> > > >>20-50mils wide. Hit the link and scroll to Figure 3. In Doug's test
> > > >>set-up, both of the two planes have been broken. Now, If one cares
> > > >>to do a crosstalk test, it looks like Doug could modify his fixture
> > > >>rather easily to do that. In the vicinity of the break, the multiple
> >
> > > >>line coupling, including between members of a diff pair jumps.
> > > >>
> > > >>
> > > >>
> > > >>
> > > >>
> > > >>If you want to perform an entertaining experiment, take a diff pair,
> >
> > > >>or just one active driver and a quiet line and route them over a
> > > >>narrow, and short break, say 0.25" by 0.02" and take four port S
> > > >>parameter measurements. Take another pair and do likewise, but keep
> > > >>extending the length of the slot, ie perpendicular to the traces by
> > > >>a factor of 2 with each test. Even though the width of the gap is
> > > >>short, by the time that slot becomes an inch or two long the band of
> >
> > > >>frequencies where coupling is fairly strong will be pretty wide.
> > > >>
> > > >>http://emcesd.com/tt2005/tt010105.htm
> > > >>
> > > >>Regards,
> > > >>
> > > >>Steve
> > > >>
> > > >>
> > > >>At 04:30 PM 1/9/2005 -0800, Lee Ritchey wrote:
> > > >>
> > > >>>Just noticed that you call a 5 cm break relatively small. Does that
> >
> > > >>>mean 5 cm in width?
> > > >>>
> > > >>>Lee W. Ritchey
> > > >>>Speeding Edge
> > > >>>P. O. Box 2194
> > > >>>Glen Ellen, CA 95442
> > > >>>Phone- 707-568-3983
> > > >>>FAX- 707-568-3504
> > > >>>
> > > >>>I just used the energy it took to be angry to write some blues.
> > > >>>Count Basie
> > > >>>
> > > >>>
> > > >>>
> > > >>>>[Original Message]
> > > >>>>From: Doug Smith
> > > >>>>To: SI-List
> > > >>>>Date: 1/8/2005 5:23:26 PM
> > > >>>>Subject: [SI-LIST] risetime effects of plane breaks
> > > >>>>
> > > >>>>I think most of us know not to route signals over plane breaks on
> > > >>>>PWBs as all kinds of bad things can happen when this occurs in a
> > > >>>>layout. But, how do you convince co-workers or your boss that a
> > > >>>>new design needs to avoid doing this even if added expense or
> > > >>>>project delay is required? Experimental data can be the key and
> > > >>>>this month my Technical Tidbit shows what happens to signal
> > > >>>>risetime if the signal crosses a plane break.
> > > >>>>
> > > >>>>Crossing Ground Plane Breaks - Part 4
> > > >>>>Risetime Effects on Signals
> > > >>>>
> > > >>>>Abstract: Signals that cross ground plane breaks on printed wiring
> >
> > > >>>>boards (PWBs) experience degradation as well as cause EMI
> > > >>>>problems. Significant degradation of signal risetime is shown to
> > > >>>>occur, even with a relatively small ground break of five cm at
> > > >>>>risetimes on the order of 300 ps.
> > > >>>>
> > > >>>>The link to the article is the picture of the experimental test
> > > >>>>setup at the bottom of the home page at http://emcesd.com .
> > > >>>>
> > > >>>>Doug
> > > >>>>--
> > > >>>>-------------------------------------------------------
> > > >>>>___ _ Doug Smith
> > > >>>>\ / ) P.O. Box 1457
> > > >>>>========= Los Gatos, CA 95031-1457
> > > >>>>_ / \ / \ _ TEL/FAX: 408-356-4186/358-3799
> > > >>>>/ /\ \ ] / /\ \ Mobile: 408-858-4528
> > > >>>>| q-----( ) | o | Email: doug@xxxxxxxxxx
> > > >>>>\ _ / ] \ _ / Website: http://www.dsmith.org
> > > >>>>-------------------------------------------------------
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