[SI-LIST] Re: resend: s2ibis2 extreme currents

Many people do the same thing.

Tom Dagostino
Teraspeed Consulting Group LLC
503-430-1065
tom@xxxxxxxxxxxxx
www.teraspeed.com

-----Original Message-----
From: si-list-bounce@xxxxxxxxxxxxx
[mailto:si-list-bounce@xxxxxxxxxxxxx]On Behalf Of Goodrich Robert-ra3862
Sent: Thursday, June 17, 2004 11:16 AM
To: si-list@xxxxxxxxxxxxx
Subject: [SI-LIST] Re: resend: s2ibis2 extreme currents


Don't know if this is necessarily PC, but in order to get rid of the
warnings in the past I have replicated the spice diode models locally and
added some (0.3 - 0.5 Ohms) series resistance to the model - whatever value
gives you an "expected" value of current at a slightly greater value of Vt
above/below the rail.  The problem is that in most digital CMOS processes
the forward biased diode characteristics are not modeled realistically (or
at all) because in digital circuits this isn't an important characteristic.
The "knee" or turn-on characteristic is important, but beyond that it's not
important to the digital library. Regards,
--Rob Goodrich, Freescale Semiconductors, Inc.

-----Original Message-----
From: si-list-bounce@xxxxxxxxxxxxx [mailto:si-list-bounce@xxxxxxxxxxxxx] On
Behalf Of Ingraham, Andrew
Sent: Thursday, June 17, 2004 11:44 AM
To: steimle@xxxxxxxxxxxxx; si-list@xxxxxxxxxxxxx
Subject: [SI-LIST] resend: s2ibis2 extreme currents


(Sorry if this is a repeat ... my first reply doesn't seem to be getting to
the list, so I'm sending it again.)

Your IBIS model faithfully duplicates what the SPICE model did under those
circumstances.

It is probably just a warning (not an error), letting you know that the
currents were on the high side for real silicon, but it doesn't necessarily
mean something is wrong.  That part of the SPICE-to-IBIS translation is
stressing the silicon in a way that it may not normally be used.

If you were happy with the SPICE model before, then be happy with the IBIS
model too.

On the other hand, this experience has probably taught you that your old
trusty SPICE model was probably somewhat limited in its handling of extreme
overshoots.  Most of the time this isn't an issue for anybody, because the
model (even though its clamp currents may have been impractically large) did
direct the simulation to do the right thing (i.e., clamp the voltage), and
the waveform might be essentially the same whether the clamping current was
0.7A or 70A.  IBIS won't care (in spite of its warning).  However, in some
cases the time-domain results might not correlate well with real silicon,
and then you would want to fix the SPICE model.

The justification for fixing it is NOT because the IBIS model causes those
warnings.  It's because the SPICE model wasn't accurate in the first place.

Regards,
Andy



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