[SI-LIST] Re: replacing ECL ??

Hi All,

I think that this is a very important lesson
for some new (and perhaps old) folks to be aware 
of.  That being, do not assume that the application
note that you have in front of you is passed down
from the gods above, implemented in volume, checked 
over PVT or checked at all.  Often times a healthy 
amount of skepticism  can be a very valuable signal 
integrity tool, especially when 'blindly' copying 
someone's design, app note or not.  In the same way
that a model can only be trusted so far, one must 
perform due diligence to assess exactly how good an
application note is.  I am sure that many of the folks 
on this list have sent a kind email back to a chip 
manufacturer letting them know that their calculations,
topologies, assumptions etc were less than accurate,
dead wrong, or yes.  However, before the flamefest 
erupts, there are a great number of vendors who do a fantastic
job, generating app notes that are properly researched,
consider variations in process, temp, V, other, are
correct and extremely useful.  My point is to review 
the data, question when you see something that doesn't 
seem quite right, find out if anyone including the vendor
has followed it, and proceed when you 
believe everything appears correct.  When push comes 
to shove, the engineer is responsible for the operation
of the circuit and not the generator of the app note.

The best ones I like are where a vendor is figuring 
timing and assumes best case timing in the setup case
and worst case timing in the hold case or vice versa.

Actual implementation is left as an exercise for the reader.

Getting back to Mike's issue.  Now that it sounds
like things have been implemented, are you stuck with an
ecl source or do you have the ability to rethink everything
from scratch.  This may make a difference in what the 
best way to solve this opportunity is.

Please advise,

best regards,

Michael C. Greim 
MTS - Signal Integrity 

SONUS Networks 

Voice: +1 978 589 8336
Fax: +1 978 392 9118

email :   mgreim@xxxxxxxxxxxx <mailto:mgreim@xxxxxxxxxxxx>  
Internet:   www.sonusnetworks.com <http://www.sonusnetworks.com> 
The Voice of the New Public Network.(tm)

The time is gone, the email's over 
Thought I'd something more to say
 
And All this science they don't understand
It's just my job six days a week
 




-----Original Message-----
From: Robison Michael R CNIN [mailto:Robison_M@xxxxxxxxxxxxxx]
Sent: Monday, November 26, 2001 1:44 PM
To: si-list@xxxxxxxxxxxxx
Subject: [SI-LIST] replacing ECL ??



hello,

we recently put together an ECL clock divider and
phase shifter printed circuit board.  the circuit
was taken from a design application, which has since
proven to be somewhat of a joke.  the company rep
stated that although they had published the app note,
the circuit was theoretical and would probably not 
work at the advertised speed.  hahaha.  jokes on us.

we have 576MHz coming onto the board, where it is
divided down into a phase-locked 32MHz, 16MHz, and 
2MHz signal clock.  we plan on getting around gate-
delay by using a digitally tuned phase shifter to 
shift divided pulses to sync with the 576MHz.

i have heard that ECL is often a poor choice for 
designs today because of other newer technologies
with better noise margins.  

could you please recommend a good technology to use,
and note a source for information and acquisition?

thank you, miker 
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