[SI-LIST] Re: remove non-functional pads: measuring via capacitance with TDR

Hi Steve,
I'm surprised at your response - perhaps I'm misunderstanding what
you're saying.  I believe WL's original assertion that, when measuring a
parasitic C with a faster TDR step, you'll see a deeper dip, is correct.


WL,
That does not, however, mean you'll measure a larger capacitance.  You
should find that, regardless of the risetime, the total area of the dip
remains constant, and is a function of the total excess capacitance.
With a fixed capacitance, a fast rise-time TDR will show a deep, narrow
dip; a slow rise-time will show a shallow, wide dip.  The area of the 2
dips should remain constant.  In the paper you referred to, this
manifests itself as the integration operation; by measuring the area of
the dip, Agilent is able to calculate excess capacitance.

Given this, if you measure the apparent impedance of the 2 dips directly
from the screen (using rho), the TDR with a fast rise-time will indicate
a lower impedance for the capacitive dip than that for the slower
rise-time.  This is why it's important to indicate not only the apparent
impedance change of a discontinuity, but also the total apparent
duration of that discontinuity.

Jeff Loyer


-----Original Message-----
From: si-list-bounce@xxxxxxxxxxxxx [mailto:si-list-bounce@xxxxxxxxxxxxx]
On Behalf Of steve weir
Sent: Tuesday, April 06, 2004 9:55 PM
To: lin-wl_wang@xxxxxxxxxxx; zasio@xxxxxxxxxxxxxxxxxxx
Cc: si-list@xxxxxxxxxxxxx
Subject: [SI-LIST] Re: remove non-functional pads: measuring via
capacitance with TDR

Lin, No, that's not right.  The impedance of a pure capacitance falls
with=20
decreased rise time.  The apparent capacitance does not increase.
Steve.
At 11:42 AM 4/7/2004 +0800, lin-wl_wang@xxxxxxxxxxx wrote:
>Hi John,
>
>Thanks for your sharing! I think this is a very good comparison.
>
>I have some questions on your experiment. What rise time did you use in
=3D
>TDR measurement? If the rise time is fast enough, the small parasitic C
=3D
>of via can be identified from TDR waveform. I happen to see an article
=3D
>in following site:
>http://cp.literature.agilent.com/litweb/pdf/5988-6505EN.pdf
>with title: Measure Parasitic Capacitance and Inductance using TDR
>
>So I think the C of via can also be estimated using your TDR result. =
=3D
>I'll prefer this method than using a C meter, the reasons are on the =
=3D
>first page of this article.=3D20
>
>Another thing I'm thinking is that with faster TDR step, you'll see a =
=3D
>deeper dip, so a bigger capacitance value. Does this mean there's no =
=3D
>fixed value for capacitance of via? It's always changing with TDR rise
=3D
>time or bandwidth?
>How do you think about this?
>
>Thanks!
>
>-WL
>
>-----Original Message-----
>From: John Zasio [mailto:zasio@xxxxxxxxxxxxxxxxxxx]
>Sent: Tuesday, April 06, 2004 2:57 AM
>To: WANG,LIN-WL (A-Singapore,ex1)
>Cc: si-list@xxxxxxxxxxxxx
>Subject: Re: [SI-LIST] Re: remove non-functional pads: any improvement
>be seen
>
>
>WL,
>
>I choose to remove non-functional pads from all high speed vias. If =3D
>space
>permits I also design the power plane anti-pad so that the via looks =
=3D
>like
>a 50-Ohm coaxial transmission line.
>
>Example: OC48 line card (2.448 Gb/s)
>         26-layer FR406 PC Board=3D09
>                 12 PWR/GND planes
>                 12 Signal planes
>                 2 Surface pad layers
>         Agilent OC48 SFF Transceiver
>
>Via characteristics:
>                                 Standard        50-Ohm
>         Board Thickness         102-mil         102-mil
>         Drilled hole dia.       13-mil          13-mil
>         Signal pad dia.         25-mil          25-mil
>         Pwr anti-pad dia.       35-mil          64-mil
>
>         Capacitance
>           With 12 signal pads   1.304 pF        0.756 pF
>           With  1 signal pad    0.829 pF        0.501 pF
>
>The 2.448 Gb/s path from the transceiver to the SerDes has all the vias
>on a 100-mil pitch. These can accommodate the 64-mil antipad. I place =
=3D
>the
>signal wires on the signal plane near the bottom of the PCB. This =3D
>creates
>a path from the component (top side of PCB) to the signal wire that =3D
>looks
>like 50-Ohms. The via is so clean the it does not show up on a TDR
>measurement.
>
>For large BGAS with vias on a smaller pitch, I use the standard via but
>without non-functional pads.
>
>Every one of my PC Boards has a built in test coupon with examples of =
=3D
>these
>vias. I use coax probes into the vias and measure the capacitance at 1
=3D
>MHz
>with a Boonton capacitance meter designed for measuring semiconductor =
=3D
>devices.=3D20
>It will measure 1.0pF with a 0.01pF accuracy.
>
>Regards,
>John Zasio
>
>=3D09
>=3D09
>
>lin-wl_wang@xxxxxxxxxxx wrote:
>
> > Thanks to all who responded!
> >=3D20
> > I checked with PCB fabricator again. They can easily delete all
unused =3D
>=3D3D
> > pads, but it would be time-consuming to selectively delete some of =
=3D
>them.
> >=3D20
> > Just curious, do you always choose to remove non-functional pads for
=3D
>GHz =3D3D
> > signal lines? And How much improvement have you seen?
> >=3D20
> > Thanks!
> > -WL
> >=3D20
> > -----Original Message-----
> > From: si-list-bounce@xxxxxxxxxxxxx
> > [mailto:si-list-bounce@xxxxxxxxxxxxx]On Behalf Of Chris McGrath
> > Sent: Friday, April 02, 2004 10:58 PM
> > To: si-list@xxxxxxxxxxxxx
> > Subject: [SI-LIST] Re: remove non-functional pads
> >=3D20
> >=3D20
> >=3D20
> > Our board house uses Boardstation and it is my understanding that
> > turning unused pads off (removing them) is a configuration option.
=3D
>I'm
> > not sure if you can selectively do it, but I know that this is not
> > difficult to do if you want all pads removed.
> >=3D20
> > -Chris
> >=3D20
> >=3D20
> >>-----Original Message-----
> >>From: lin-wl_wang@xxxxxxxxxxx
[mailto:lin-wl_wang@xxxxxxxxxxx]=3D3D3D20
> >>Sent: Thursday, April 01, 2004 8:48 PM
> >>To: si-list@xxxxxxxxxxxxx
> >>Cc: lin-wl_wang@xxxxxxxxxxx
> >>Subject: [SI-LIST] remove non-functional pads
> >>=3D3D3D20
> >>=3D3D3D20
> >>Hello,
> >>=3D3D3D20
> >>I would like to know how to remove those non-functional =
pads=3D3D3D20
> >>in order to reduce via capacitance? Manually or =
automatically=3D3D3D20
> >>by layout software?
> >>=3D3D3D20
> >>Currently I'm thinking of two methods.
> >>1.In layout design, define via in the way that:
> >>(1) on all inner layers, pads defined as diameter=3D3D3D3D0 or =3D
>12,=3D3D3D20
> >>drilling hole=3D3D3D3D12mil(for example)
> >>(2) on an inner layer where trace is connected, pads =
defined=3D3D3D20
> >>as diameter=3D3D3D3D20mil, drilling hole=3D3D3D3D12mil
> >>=3D3D3D20
> >>To what I understand, the unnecessary pads will be removed,=3D3D3D20
> >>and the pads used to route out the traces will remain. But=3D3D3D20
> >>there're many errors when generating the gerber due to this=3D3D3D20
> >>removal. Don't feel comfortable with the errors. We're now=3D3D3D20
> >>using PADS PowerPCB, do not know if the software has a=3D3D3D20
> >>function to remove these pads automatically. Hasn't got =
reply=3D3D3D20
> >>from vendor yet.
> >>=3D3D3D20
> >>2. or manually remove the pads in gerber file, but there're=3D3D3D20
> >>quite a lot.=3D3D3D20
> >>How do you think about the two method? Is there any better=3D3D3D20
> >>way to remove?
> >>=3D3D3D20
> >>Thanks!
> >>-Wang Lin
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Steve Weir
Teraspeed Consulting Group LLC
2926 SE Yamhill St.
Portland, OR 97214
(503) 239-5536
http://www.teraspeed.com
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Teraspeed(SM) is the service mark of Teraspeed Consulting Group LLC


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