[SI-LIST] regarding PCI-Express clocking scheme - dazzled & confused

Hi all,
I'm working on a PCI-E board for quite a while now, and I'm trying to
figure something out here, regarding the clock scheme of the PCI-E.
I've looked through the spec. of PCI-E and from wondering around the
net i found a few things that don't match up:

1. I understand that the transmission rate is 250 MB/S/lane, hence, if
I have x16link, then the tx rate will be 4GB/S/lane, BUT, i've read in
few places (including the Spec.) that the idea in PCI-E is that one
does not transmit clock, but rather 8b10b encoded data, and from this
the other end re-create the recieve clock. how does that settle?

2. also, there's a 100MHz clock which is called a reference clock,
that IS transmitted... how does that settle with remark 1) ?

3. furthermore, what is the 2.5Gb/s tx rate, which ussually, when
people talk about PCI-E, they through it in the air...? 2.5Gb/s is not
250MB/s/lane...

if anyone will be able to explain all that to me ,it will be great,
cause i'm all messed up around here...
Thanks guys and girls!
Roy
------------------------------------------------------------------
To unsubscribe from si-list:
si-list-request@xxxxxxxxxxxxx with 'unsubscribe' in the Subject field

or to administer your membership from a web page, go to:
http://www.freelists.org/webpage/si-list

For help:
si-list-request@xxxxxxxxxxxxx with 'help' in the Subject field

List FAQ wiki page is located at:
                http://si-list.org/wiki/wiki.pl?Si-List_FAQ

List technical documents are available at:
                http://www.si-list.org

List archives are viewable at:     
                http://www.freelists.org/archives/si-list
or at our remote archives:
                http://groups.yahoo.com/group/si-list/messages
Old (prior to June 6, 2001) list archives are viewable at:
                http://www.qsl.net/wb6tpu
  

Other related posts: