[SI-LIST] Re: pwr-gnd loop inductance measurement

What you have to ask yourself is given the presence of degassing mesh holes
in build up planes and highly swiss cheesed I/O escape underneath the die,
is the core pwr/gnd current really run horizontally through the package
planes (almost like a good old wirebond peripheral power distribution) or
the core power/gnd distribution is really through the vertical current path
straight through the power/gnd vias up to the die and distributed with the
power/gnd grid on die. I believe the later is dominant with or without
sufficient on die coupling cap.

Rather than shorting the vdd balls and vss balls, you might want to consider
having a die with power/gnd bumps shorted and do the reverse measurement.
Loop inductance measurement at the balls will show you whether the pins
directly underneath the die is the low impedance path as I claimed or the
pins spread through out the package has better impedance as you think. 
 

-----Original Message-----
From: Jean Audet [mailto:jaudet@xxxxxxxxxx]
Sent: Thursday, October 24, 2002 6:19 AM
To: chris.cheng@xxxxxxxxxxxx; si-list@xxxxxxxxxxxxx
Subject: Re: [SI-LIST] Re: pwr-gnd loop inductance measurment


Depending the package you are using, you may have current flowing through
the plane or power strap... This may be the case for some particular design
using the buildup technology. and you are right , on-chip decap are used
but for some application you can not put as many decap as you want and you
may be limited in space....

And in my case I'm interrested to see the impact of a new SLGA interconnect
versus other LGA connector...How good is versus others

Jean Audet
Electrical Analysis
InterConnect Products IMD
IBM Burlington
Tel: 802-769-0835, tie line: 446-0835
Tel: 450-534-6317, tie line: 552-6317
E-mail: jaudet@xxxxxxxxxx

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