[SI-LIST] Re: (probably naive) FPGA PDS questions

Glenn-

Good questions. Unfortunately the definitve answers are anything but 
simple. As you and others have mentioned, there are several camps of 
thought on how to accomplish effective decoupling over a broad frequency 
range. (multiple values carefully selected, use just a couple values, 
use only one value, use controlled impedance decoupling, the shotgun 
approach, and probably a few others).

Personally, I am a proponent of the use of multiple values selected to 
generate a lo-Z composite impedance profile. (while I was at Sun our SI 
staff did considerable work over the years to develop and validate that 
methodology). I'm not going to get into the technical details now as 
this has been covered ad-nauseum in the past in multiple message threads 
that can be searched out in the archives.

Regarding determining the transient current of a chip, this has always 
been a sticky issue. It is one of those numbers that is usually (almost 
always??) not documented in the data sheets. I think this is because a 
lot of vendors don't know the number themselves. You can determine this 
number with some effort if you have an operating design, or it can be 
determined by simulation at the device level by the silicon designers. 
If you don't have either of those avenues open to you, a couple of 
ballpark figures that are better than nothing are: for CMOS logic , 50% 
Idc, for CPU core voltages from 20%-50% Idc . Others may have better 
estimates. It depends on the chip technology, the circuit architecture 
architecture etc., etc..... CPUs are different than logic which are 
different than Serdes's which are different than memory which is 
different than ......  FPGA's need to be evaluated on a case by case 
basis based on the circuitry programmed within them.


On your question on the planar capacitance, the anti-resonance you are 
seeing is definitely real and not a simulation artifact. It is a 
function of the parallel plate PCB capacitance resonating with the 
mounted inductances of all your decaps in parallel (a very small 
inductance). The frequency of the anti-resonance is usually high enough 
(100 MHz and up) that it isn't so much an SI issue as it is a EMI/EMC 
issue. You really can't get rid of the resonance, but there are 
techniques to manage it to somewhat minimize the amplitude of the 
impedance peak. If you include a model of your chip package in the  
simulation the anti-resonance becomes even nastier to deal with. The 
bright side is that if you look at the impedance profile at the Vdd/Vss 
nodes at the die, the anti-resonance peak is almost invisible (usually) 
as compared to looking at it at the package/pcb interface.


Regarding your online tool: very nice little applet. You've replicated a 
small part of our original in-house Java version of decaptool we 
developed at Sun about 5 years ago. After we patented it we licensed the 
concept to Cadence. The methodology is now available in Cadence 
Specctraquest as the Power Integrity Module. The most important part of 
the tool is the models of the decaps. Many capacitor vendors are now 
doing a much better job a measuring ESL and  ESR to produce decap models 
you can believe in. Early data (from as near as 3 years ago) found on 
vendor sites and data sheets should be taken with a grain of salt as the 
measurement techniques to determine ESR and ESL were not what they 
should have been throughout the industry. It requires good fixturing, 
careful technique, accurate lab equipment, proper extraction technique 
and a lot of statistical number crunching to come up with good element 
values you can believe in. For certain simulations, even the traditional 
RLC model that almost everyone uses isn't accurate enough and you need 
to go to a more complicated model such as the 'stacked-cap' model that 
Larry Smith @Sun has published. It basically looks at the decap as a 
transmission line structure rather than a lumped element approximation.

One last comment, the simulations being performed by your online tool 
are what we call 'single-node' simulations where all the decaps are 
electrically connected to a single node in the simulator deck. This is 
the simulation we tend to use most often as it is sufficiently accurate 
to determine the impedance profile below the package resonance frequency 
(in the 30MHz-100 MHz range usually). Above that range where pcb 
resonances become an issue you need to do a multi-node analysis which 
incorporates a plane model that allows you to define the  spatial 
location on the PCB of the various components. For CPU core simulation, 
these high frequency effects are of most interest for EMI reasons. 
Impedance issues at these high frequencies seen at the die can only be 
effectively dealt with using on-die and on-package decoupling. Just 
about anything you do at the PCB level won't help out at the die due to 
the low pass nature of the package. For i/o problems the performance of 
the decoupling network at high frequencies can be important from a SI 
standpoint as well.


-Ray Anderson



Glenn Judd wrote:

>  Without desiring to rehash the "Decoupling capacitors" thread from
>  2002 (a very helpful thread), I have a=20 few PDS/decap questions:
>
>  Question 1
>
>  I'm designing a PDS for an FPGA right now, but I'm=20 unsure of my
>  target Z since I'm unsure what transient current my FPGA
>  (XC2V250FG256) is capable=20 of drawing. Xilinx's XAPP623 doc
>  mentions using measurements to determine this, but doesn't mention
>  how to do this before fab.=20
>
>  What they do mention is to use the number of pins=20 as a rough guide
>  on the number of caps. Using that guide, I've come up with the
>  following:=20 http://gs229.sp.cs.cmu.edu/vcc1.5.jpeg. I'm concerned,
>  however, that that may not be good enough, but getting lower would
>  require more caps which would seem to fly in the face of the
>  1-cap-per-pin rule (the design shown is already using somewhat=20
>  more than 1-cap-per-pin).
>
>  Question 2
>
>  My analysis also seems to indicate that life might be better
>  _without_ planar capacitance as shown on this plot (red is without
>  planar capacitance):=20
>  http://gs229.sp.cs.cmu.edu/vcc1.5withoutPlanarCap.jpeg (I plan on
>  running the FPGA @ 200MHz.) Is that right? This is counterintuitive.
>  I'm guessing that since real anti-resonance spikes (i.e. not using my
>  tool's "generic" model) aren't nearly so bad, this plot might be
>  misleading.
>
>  Question 3
>
>  I've frequently seen designs that use only 47uf, 4.7uf, and 0.1uf
>  capacitors. I've also seen many people advocate using only 1 high
>  speed decap size to mitigate anti-resonance issues. My experiments=20
>  with my homebrew impedance analysis tool (see below)=20 seem to
>  indicate that without using several values of caps, Z will be quite
>  high over a broad range of frequencies. In addition to several high
>  frequency cap values, low Z in the lower frequencies required a
>  low-ESR bulk capacitor > 200uf. How are those designs working? I
>  understand that fewer values =3D fewer anti-resonance=20 peaks, but I
>  can't see how a decently low Z can be met over a broad range of
>  frequencies with this approach (without _huge_ numbers of
>  capacitors). (I'm guessing that this is a point of controversy, so
>  replying directly to me on this point is probably best since I don't
>  want to re-ignite something that's probably dealt with somewhere in
>  the archives that I couldn't find.)
>
>  Thanks.
>
>  Glenn
>
>  p.s. The plots above were generated with a simple tool=20 that I've
>  tossed together for doing the obvious Z calculation, but using some
>  real cap data. The tool is current up at:
>  http://gs229.sp.cs.cmu.edu/PDSAnalyzer.html. It requires JDK1.4+ or
>  JavaPlugin etc. (It won't be up =20 permanently.)
>
>
>
.


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