[SI-LIST] Re: power planes (4-layer-board)

Daniel, a ferrite bead is a normal inductor.  It is characterized by:

1. Very linear inductance, IE high Q up to 20MHz for high nickel 
ferrites typically used for EMI suppression.
2. A resistive impedance from somewhere around 5-20MHz out into the 
100's of MHz.
3. A capacitive impedance from about an octave beyond the peak impedance 
frequency and higher.

If you pick a ferrite that has a very high resistance rating, you can 
get burned a few ways:

1. Very low Fco that may be excited by things like switching power 
supplies. 
2. Very high Zchar at Fco, compounded by high Q at Fco.
3. High DCR.
4. Poor attenuation in the high 100's of MHz to low GHz.

The idea of layer 3 routing is that layer 4 ground fill will act as an 
RFI shield.  If you follow that practice, adjust the trace widths on 
layer 3 down to maintain the right impedance.  Given that layer 2 is so 
far away, the adjustment won't be much.

Steve.

Daniel Bauer wrote:
> David, 
>
> thanks for your answer. I`ve read some application notes whether it would be 
> desireable to use power planes or not... As you said, there many different 
> aspects about this subject. But I also tend to avoid huge power planes which 
> exactly mirror the ground plane. Separating a large plane into individual 
> smaller planes (connected by an ferrite bead), pushes the resonances into the 
> GHz region (and I`m out of trouble...) Do you think that a ferrite bead with 
> an 1000 ohm impedance would be ok or is it better to use "normal" inductors? 
>
>   
>> A stackup option is
>>  
>> Components
>> 1: Some signal traces, ground fill only if well stiched to gnd
>> 2: GND
>> 3: Fast signals (high EMI risk), other signals, some power and ground fill
>> 4: Power, slow signals (low EMI risk), power, ground fill.
>> Some decoupling on the back side if the space was too little on the top side
>>     
>
> There`s an article from you about ground fills "PCB ground fill design 
> guidelines for radiated EMI" - but at the moment I`m not a member of the IEEE 
> group. 
>
> You prefer to route the critical signals on layer 3 - then the return current 
> don`t have to change the layer (two thumbs up). Provided that I don`t use 
> ground fills on the outer layers, the return current is probably only in the 
> ground plane on layer2. When I use ground fills, then they will also carry 
> the return current - lower impedance -> therefore, use of many stitching 
> vias. And all small power planes have to be installed on the third layer, 
> otherwise I`m not able to avoid the return current on these small planes. 
>
> However, I`m a little bit unsure about the signal integrity versus changing 
> the trace impedance. When I route some traces on layer 3 (bottom layer 
> includes a few ground fills) - then the impedance will change (stripline - 
> embedded microstrip) as well as when the trace will be on the top layer 
> (microstrip).  When I route all signal traces on the bottom and top layer, 
> insuring that the adjacent inner layer is a ground plane, the impedance will 
> be the same (besides the via).  
>
>
>   
>> I suggest to simualte a trace-routed power distribution system. This is not 
>> so difficult as no full wave solution is needed. SPICE will just work fine.
>>     
>
> What do you exactly mean by "trace-routed power distribution system"? 
>
> best regards
> Daniel
>
>
>   
>> Daniel,
>>  
>> It is quite common not to use power planes in 4-layer boards. There are 
>> reasons for using power planes and reasons to avoid them.
>>  
>> Power planes maybe needed:
>>  
>> a) Some ICs need a low power-GND impedance for SI reasons. The effect of 
>> having a power plane and local decoupling or only local decoupling starts to 
>> be relevant between 100 - 1 GHz, depending on the 
>>     spacing between the power plane and GND (typically in a 4-layer board 
>> very large), the placing, size and connection of local decoupling, the use 
>> of mutual inductance between vias to reduce the apparent
>>     inductance in the loop formed by the decoupling capacitor etc.
>>  
>>     The IC interconnect forms an inductor and the on-die capacitance maybe 
>> pretty large, values from 100pF (very small) to 10nF (typical DSP) to uF 
>> occur. 
>>     Thus, the interconnect inductance (from as small as 50pF to a few nH) 
>> and the on-die capacitance forms a low pass filter. The high frequency 
>> current from switching is provided
>>     from on-die capacitance. Below some transition frequency, mabye 10 MHz - 
>> 500Mhz the charge is provided by the PCB. Without knowing more about the IC, 
>> the stackup etc.
>>     it is hard to say where the transition occurs. But overall, in very many 
>> cases there is no need for power planes from the SI point of view, as the 
>> effect of the power planes is in 
>>     a frequency range in which the IC uses on-die capacitance to provide 
>> charge. In a 4 layer board, if layer 2 is used for GND and layer 3 for power 
>> there maybe about 40 mil spacing
>>     between the planes, making the power-gnd plane arrangement to be not so 
>> effective and the via connections releatively long. Thus, there is a good 
>> chance that a power plane does
>>     not gain from an SI point of view.
>>  
>>     One should also distinguish between analyzing core VDD current and I/O 
>> VDD current. 
>>  
>> b) It the currents are very large a power plane is needed. For example, this 
>> Pentium may need 50Amp at 1.3V. 
>>  
>> c) Sometimes there are so many connections that it is simply very difficult 
>> to run power traces. It is not uncommon to have a small power plane under a 
>> BGA and local decoupling, but no larger power
>>     plane. This way it is easy to connect all the balls that need power to 
>> the local decoupling capacitors, but no large plane is used.
>>  
>> d) I think often power planes are used, just because it is (it was?) 
>> standard practise, also it is faster to use power planes, as less traces 
>> need to be routed.
>>  
>>  
>> Power planes also cause problems
>>  
>> e) EMC. For EMI it is much better to avoid planes. They form relatively 
>> large antennas (even a few mV are a problem) if there are no other planes to 
>> shield and no enclosure to shield. In many
>>    cases people have designed PCBs with and without power planes (keeping 
>> all component locations the same) and compared teh EMI. I am only aware of 
>> cases in which this improved the
>>    EMI. 
>>  
>> f) Routing space. Less space used for power planes allows better routing.
>>  
>> g) Shielding clock traces. One can now rout a clock trace in layer 3 and 
>> have ground on layer 4 and some stitching, this way the clock trace is 
>> shielded. This is possible for pretty much all
>>     fast (high EMI risk) traces. Thus, this contributes to the reduction of 
>> EMI
>>  
>>  
>>  
>> A stackup option is
>>  
>> Components
>> 1: Some signal traces, ground fill only if well stiched to gnd
>> 2: GND
>> 3: Fast signals (high EMI risk), other signals, some power and ground fill
>> 4: Power, slow signals (low EMI risk), power, ground fill.
>> Some decoupling on the back side if the space was too little on the top side
>>  
>> It is important to stich the ground fills well, otherwise they form 
>> resonators which can lead to EMI problems, also the ground fills in layer 4 
>> now carry the return current for the fast signals (as the spacing to them is 
>> much smaller than the spacing to the ground plane). Thus, to control the 
>> return current path vias need to be placed close to the transistions.
>>  
>>  
>> There are some risk in routed power.
>> The traces are transmission lines and they transform the impedance from one 
>> end to the other, thus, they can cause resonances. If no ferrite beads are 
>> used the resonances are at higher frequencise (> 100 Mhz), but if ferrite 
>> beads are used one needs to be aware that those beads are pretty high Q 
>> inductors at lower frequencies. Thus, one can form resonating circuits in 
>> the low MHz range, or hundreds of kHz. Those can cause functionality 
>> problems, or, even worse, hit the same frequency as a swiched power 
>> converter. 
>>  
>> I suggest to simualte a trace-routed power distribution system. This is not 
>> so difficult as no full wave solution is needed. SPICE will just work fine.
>>  
>>  
>> A couple of papers have been published on the avoidence of power planes, 
>> mainly for EMI reasons. Please contact me davidjp@xxxxxxx for further 
>> information.
>>
>> Regards,
>>  
>>   Dr. David Pommerenke
>>   MST EMClab  (former UMR EMC lab)
>>   Missouri University of Science&Technology  (former UMR)
>>   davidjp@xxxxxxx ,   573 308 2019
>>  
>>
>> ________________________________
>>
>> From: si-list-bounce@xxxxxxxxxxxxx on behalf of Daniel Bauer
>> Sent: Sat 2/14/2009 6:37 AM
>> To: si-list@xxxxxxxxxxxxx
>> Subject: [SI-LIST] power planes (4-layer-board)
>>
>>
>>
>> Hi,
>>
>> the standard layout for an 4-layer PCB is, using outer layers for the 
>> signals and the two inner layers for one ground and one power plane. The 
>> power plane seems to have a few advantages as well as disadvantages (using 
>> an 4-layer board).
>>
>> If a trace running at the top layer has to change to the bottom layer - also 
>> the return current has to change the layer (using stitched capacitors).
>>
>> What do you think about the proposal to use the third layer for ground as 
>> well as for power? On every position where an signal trace is running at the 
>> bottom layer, the third layer will be a ground plane, connected to the 
>> ground plane on the second layer.... and when there`s no trace on the bottom 
>> layer I will use an power plane on the third layer.  From this it follows 
>> that I will get some power islands on the third layer which were connected 
>> with traces on the bottom or top layer.  The complete return current should 
>> use the ground plane (which has an lower impedance) and not one of the small 
>> power islands.
>>
>> Would there be an impedance change for the signal traces changing the layer 
>> (top to bottom or vica versa) when both inner layers will use an ground 
>> plane where the signal is running?
>>
>>
>> x----------|                      (top layer - signal layer)
>>     GND   |   GND            (second layer is a complete ground plane)
>> Power    |   GND            (ground and power islands)
>>               |---------x         (bottom layer - signal layer)
>>
>> The line will show a signal trace changing from the top to the bottom layer. 
>> Both ground planes using at the inner layers, will be connected together by 
>> many vias. Could you tell me if this would be a good decision improving 
>> signal integrity? Are there any kind of disadvantages?
>>
>>
>> best regards
>> Daniel 
>>    
>>
>>
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