[SI-LIST] Re: power plane inductance



Anthony-

You can derive the inductance value you want fairly simply with
'back-of-the-envelope' type calculations thusly:

First, calculate interplane capacitance:

        Ca= (Er*Eo)/thickness  
        where Eo= 8.85pF/meter or .2248pF/inch
              Er= relative dielectric constant of board dielectric
             
         
         for example: assume 1 mil thick FR4 with Er=4
         Ca = (.2248pf/inch * 4)/1 mil = 900 pF/square inch
         
Then calculate propagation velocity:

        Velocity = Vel_of_light/sqrt(Er)
        
        so Velocity in FR4 with Er=4 would be:
        
        12e9/sec = 12 inches/nsec / sqrt(4) = 6 inches/nsec = 6e9/sec
        
Now calculate the inductance per square:

        La = 1/(Ca * Velocity^2)
        
        So for our example:
        
        La = 1 / (900pf/sq_in * (6e9)^2)
        
           = 1 / (900e-12*36e18) = 30.86pH/square
           
         Knowing this value for a 1 mil thickness you can scale it
         with thickness. so for a 4 mil stackup the inductance would be
         4X the calculated value or about 120 pH/square
         
         You can go through the numbers to convince yourself, but you
         will find the Er of the dielectric doesn't affect the inductance,
         which is a function of the thickness of the planes dielectric
         separation. 
         
         Hope this helps,
         
         Ray Anderson
         Sun Microsystems Inc.
         
         

>
>Hi Anthony:
>
>   You many want to post this question on the si_list -- I bet someone will
>have an answer for you there.
>
>  si-list@xxxxxxxxxxxxx
>
>  Regards,
>  Stephen Peters
>  Intel Corp.
>
>
>-----Original Message-----
>From: Anthony Moulds [mailto:anthony@xxxxxxxxxxxxx]
>Sent: Monday, October 15, 2001 7:37 AM
>To: ibis@xxxxxxx
>Subject: power plane inductance
>Importance: High
>Sensitivity: Private
>
>
>Sorry if this is a little off-topic but is there a formula
>for determining the inductance between two points on a power
>plane in a multi-layer pcb (pH/inch2) ? 
>
>[I need to check (quantitatively) the max placement distance of decoupling
>caps to fast logic when both are via-ing down to the power/gnd planes.]
>
>
>Thanks.
>
>Anthony Moulds
>
>

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