I've been catching up on my emails and read this thread with interest since it pertains to what I was working on last week. So I am looking for some advice to increase my understanding of this subject. Background: Last year, before I took Lee Ritchey's 2 day course, I designed a board with a DSP, fpga, PCIExpress, PCI66, and DDR2-500. Everything seems to work fine, and initial EMI scans seemed good. The stackup is S-P(+)-S-S-P(GND)-P(+)-S-S-P(GND)-S. After taking Lee's course I changed the stackup to add two ground planes next to the single power planes. Then I went for EMI scan with the original 10-layer board and the PCI bridge to PCIExpress working. It failed at 533MHz whenever the PCI bus transferred data (the PCIE bus did not emit). Looking at the board this was due to too much drive on the bridge chip for only 3 PCI loads and the PCI bus crossing a split in the power plane. The new stackup has 4 mil between the layers which are S-P(GND)-P(+)-S-S-P(GND)-P(+)-S-S-P(GND)-P(+)-S and series resistors in the PCI bus. I felt this should eliminate the PCI bus noise since the planes should be closely coupled and the overshoots eliminated. Well my coworkers finally reviewed the board and decided that I needed stitching caps where the PCI signals cross the split. I felt they were not needed due to the coupling between the planes in the new stackup. They also decided that the power plane need to be broken up so that the DDR2 signals and the PCIE reference clock had ground on the plane layer next to it. They feel that for the impedances to be correct a signal must be ground referenced to a ground plane. My understanding is that if the ground and power are well decoupled then it doesn't matter if the plane is power or ground. Since the board was late already and I did not feel these would hurt the design I went along with them. My questions to those who know more than I are: 1. Is 4 mil between plane layers enough to couple them so 66Mhz PCI and a few 100Mhz signals will couple across the gap without lots of EMI? 2. Will adding stitching caps between the positive voltages on the two sides of the split actually do any good? 3. Is breaking up the positive plane to make an area of ground on the layer next to DDR2 signals and the differential PCIE reference clock an improvement over keeping the plane intact when the planes are 4 mil apart and there are lots of 0.1 and 0.01uF 0402 caps all over the planes? I intend to test the board with and without the stitching caps here and when out at the field site for EMI scan, to determine for myself if they do anything. Of course I am kicking myself for not using 12 layers in the first place, but then it took me many years to get the company to approve me going to a class like Lee's. Any advice or knowledge you can impart will be appreciated. Rob LaMoreaux ------------------------------------------------------------------ To unsubscribe from si-list: si-list-request@xxxxxxxxxxxxx with 'unsubscribe' in the Subject field or to administer your membership from a web page, go to: http://www.freelists.org/webpage/si-list For help: si-list-request@xxxxxxxxxxxxx with 'help' in the Subject field List technical documents are available at: http://www.si-list.net List archives are viewable at: http://www.freelists.org/archives/si-list or at our remote archives: http://groups.yahoo.com/group/si-list/messages Old (prior to June 6, 2001) list archives are viewable at: http://www.qsl.net/wb6tpu