[SI-LIST] Re: plane-to-plane decoupling

  • From: Richard Jungert <r_jungert@xxxxxxxxxxx>
  • To: steve weir <weirsi@xxxxxxxxxx>, <mrose@xxxxxxxxxxxx>, <si-list@xxxxxxxxxxxxx>
  • Date: Mon, 15 Sep 2008 15:12:10 -0700

Steve.

Caps are ok but they are bi-directional and narrow band. They work great when 
you have all the frequencies figured out or in a narrow band app.  I have seen 
them work great for say 10mhz applications but then there is a 300-500 mhz tone 
causing problems what do you do?  This happens all too often on digital boards. 
 We live in a wide band world now and so that is why I partially dissagree.  

Richard 

> Date: Mon, 15 Sep 2008 14:09:05 -0700
> From: weirsi@xxxxxxxxxx
> To: r_jungert@xxxxxxxxxxx
> CC: mrose@xxxxxxxxxxxx; si-list@xxxxxxxxxxxxx
> Subject: [SI-LIST] Re: plane-to-plane decoupling
> 
> Richard, in my experience, linear regulators can be effective for 
> cleaning up PLL power on the PCB but they are usually completely 
> unnecessary.  The bandwidth of even a good linear regulator by itself is 
> still in the audio range.  If your PLL is insensitive to audio frequency 
> disturbances by virtue of a good loop, then what you are really buying 
> with the linear regulator is a very expensive series L/R that works with 
> the bypass caps on the PLL side to filter noise from the dirty digital 
> realm.  With a little care you can usually save a lot of: board 
> real-estate, money, and complication by designing a passive filter to do 
> the same or better job.
> 
> Steve.
> 
> Richard Jungert wrote:
> > Mike.
> >
> > I would recommend putting the PLL circuit near the edge of the board and 
> > also cut a power and ground plane split 270 degrees around or under the PLL 
> > circuit.  Cut them both the same shape. If you put it near the center of 
> > the board there is a very high probablility for much more jitter. 
> >
> > Also, in my experience its not a great idea to power the PLL with a common 
> > voltage. Put a small low power voltage regulator in to just power the PLL 
> > circuit and this will isolate him from the rest of the noisy digital logic. 
> >  Power and ground plane noise will sneak right into the PLL and modulate 
> > your clock. 
> >
> > I have found on three other designs that this approach is very effective in 
> > cutting down phase noise on the clock circuits.
> >
> > Another trick that cuts noise on ground/power planes is decoupling with 
> > caps out to the chassis ground.  Decouple out to the chassis ground and 
> > watch the noise decrease. This is also a trick used to supress EMC 
> > problems. 
> >
> > Richard Jungert
> >
> >
> >
> >   
> >> Subject: [SI-LIST] Re: plane-to-plane decoupling
> >> Date: Mon, 15 Sep 2008 12:14:31 -0500
> >> From: zabinski.patrick@xxxxxxxx
> >> To: mrose@xxxxxxxxxxxx; si-list@xxxxxxxxxxxxx
> >>
> >> Mike,
> >>
> >> In answer to your last question, I believe the lowest-inductance option
> >> involves capacitors placed directly between the two power planes (and
> >> not through the ground plane).
> >>
> >> That said, the scenario scares me.
> >>
> >> For many components that require multiple planes (e.g., FPGAs w/
> >> SerDes), some of their supplies are very sensitive to noise.  For
> >> example, nearly all SerDes cores have an analog supply for phase-locked
> >> loops (PLLs), and noise injected into them can severely degrade jitter
> >> performance.   Similarly, noise on the I/O supply of a parallel bus can
> >> degrade SI of the output waveform.  In many instances, the chip supplier
> >> provides guidelines for isolating such voltages, often recommending
> >> specific isolation circuits.  Adding decoupling between the various
> >> voltages will/can defeat the isolation circuits and inject noise from
> >> one plane onto the next.
> >>
> >> Although adding decoupling between the power planes will help with
> >> discontinuities of the signals traversing the split, you could be
> >> inadvertently creating other problems.  As such, I suggest you look
> >> closely at the power planes that you're about to inject noise into and
> >> ensure they are immune to outside influence.
> >>
> >> Good luck,
> >> Pat Zabinski
> >> Mayo Clinic
> >>
> >>
> >>     
> >>> Some diff pairs on L4 will cross power plane splits (actual different
> >>> power sources and loads) and I wanted to provide an effective AC path
> >>> for any common-mode return currents. I was thinking about placing some
> >>> nearby decoupling caps from plane-to-plane across the split. Do you
> >>> think it would be better to decouple from plane-to-ground on 
> >>> both sides
> >>> to steer the current through the L6 ground layer? L5 and L6 
> >>> are already
> >>> coupled through the inter-plane capacitance (they're about 
> >>> 4mils apart).
> >>> Which will provide a lower inductance path?
> >>>       
> >>  
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