[SI-LIST] Re: plane-to-plane decoupling

  • From: "Zabinski, Patrick" <zabinski.patrick@xxxxxxxx>
  • To: "Michael Rose" <mrose@xxxxxxxxxxxx>, "SI-List" <si-list@xxxxxxxxxxxxx>
  • Date: Mon, 15 Sep 2008 12:14:31 -0500

Mike,

In answer to your last question, I believe the lowest-inductance option
involves capacitors placed directly between the two power planes (and
not through the ground plane).

That said, the scenario scares me.

For many components that require multiple planes (e.g., FPGAs w/
SerDes), some of their supplies are very sensitive to noise.  For
example, nearly all SerDes cores have an analog supply for phase-locked
loops (PLLs), and noise injected into them can severely degrade jitter
performance.   Similarly, noise on the I/O supply of a parallel bus can
degrade SI of the output waveform.  In many instances, the chip supplier
provides guidelines for isolating such voltages, often recommending
specific isolation circuits.  Adding decoupling between the various
voltages will/can defeat the isolation circuits and inject noise from
one plane onto the next.

Although adding decoupling between the power planes will help with
discontinuities of the signals traversing the split, you could be
inadvertently creating other problems.  As such, I suggest you look
closely at the power planes that you're about to inject noise into and
ensure they are immune to outside influence.

Good luck,
Pat Zabinski
Mayo Clinic


> Some diff pairs on L4 will cross power plane splits (actual different
> power sources and loads) and I wanted to provide an effective AC path
> for any common-mode return currents. I was thinking about placing some
> nearby decoupling caps from plane-to-plane across the split. Do you
> think it would be better to decouple from plane-to-ground on 
> both sides
> to steer the current through the L6 ground layer? L5 and L6 
> are already
> coupled through the inter-plane capacitance (they're about 
> 4mils apart).
> Which will provide a lower inductance path?
 
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