[SI-LIST] Re: placement of decoupling caps (again)

  • From: Ray Anderson <Raymond.Anderson@xxxxxxx>
  • To: si-list@xxxxxxxxxxxxx
  • Date: Wed, 14 Apr 2004 16:19:54 -0700

Lee Ritchey wrote:
> UMR did a paper in 1995 that determined location is not important as long
> as you don't cut up the power planes.  Others have repeated those same
> tests, as have I,  and come up with the same answers.
> 
> The proponents of location matters need to do some testing to show that
> their position is valid.
> 
> Lee
> 
> Lee W. Ritchey
> Speeding Edge
> P. O. Box 2194
> Glen Ellen, CA 95442
> Phone- 707-568-3983
> FAX-    707-568-3504
> 

OK, how about a thought experiment.

Scenario one:
--------------

You've got a rather large PCB (say 24" x 24") with no cuts in the power 
planes. The board has a fast, current hungry chip (say 400  MHz clock 
rate, 80psec rise time, 50 amps of transient current) in one corner 
clocking away. Some number of appropriate decaps are located within an 
inch of the chip. Everything works OK (whatever that means...).

Scenario two:
-------------

You've got a rather large PCB (say 24" x 24") with no cuts in the power 
planes. The board has the same fast, current hungry chip in one corner 
clocking away. The same decaps as were used in scenario one are now 
located at the opposite corner of the board (about 34 inches away). Does 
everything still work OK?


Without actually doing the experiment, I'll go out on a limb and venture 
to say no. Granted, this is an extreme contrived example, but I really 
don't think you can make a blanket statement and say that the location 
of the decoupling capacitors on a PCB is a "don't care" decision.


-Ray Anderson
Sun Microsystems Inc.

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