[SI-LIST] Re: placement of decoupling caps (again)
- From: "Lee Ritchey" <leeritchey@xxxxxxxxxxxxx>
- To: "Paul Mobbs" <paul@xxxxxxxxxxxxx>, steimle@xxxxxxxxxxxxx,si-list@xxxxxxxxxxxxx
- Date: Wed, 14 Apr 2004 15:36:06 -0700
Doesn't all of this sound a little bit arbitrary? In fact it is. In very
few, if any, cases have IC manufacturers done any real engineering to
determine how many an what kind of capacitors are needed. There is a well
established methodology for determining the right answers. Wish the IC
manufacturers would use it.
Lee
Lee W. Ritchey
Speeding Edge
P. O. Box 2194
Glen Ellen, CA 95442
Phone- 707-568-3983
FAX- 707-568-3504
I just took the energy it took to be angry and wrote some blues.
Count Basie
> [Original Message]
> From: Paul Mobbs <paul@xxxxxxxxxxxxx>
> To: <steimle@xxxxxxxxxxxxx>; <si-list@xxxxxxxxxxxxx>
> Date: 4/14/2004 3:12:34 PM
> Subject: [SI-LIST] Re: placement of decoupling caps (again)
>
> Chip vendors will often produce app notes on this subject. I think it used
> to be recommended that # of power pins = # of decoupling caps, but I think
> it is no longer valid for BGAs (or maybe just impractical!). I think the
> idea is to get the decoupling as close to the power pins as possible. For
> small boards with lots of parts you often find that you don't have room
for
> all the decoupling that is "recommended", so you just put as much as you
> can. I have also heard of people not installing any decoupling and not not
> having a problem.
>
> Cypress has a good read called "Perfect Timing: A Design Guide for Clock
> Generation and Distribution".
>
> In the end it is a bit of personal experience, a bit of black magic, and a
> large amount of luck... but I'm sure there is someone out there who has a
> "real" answer for you!
>
> Good luck!
> Paul Mobbs
> Mobbs Engineering
> Email: paul@xxxxxxxxxxxxx
> Voice: (415) 563-1454
>
> ----- Original Message -----
> From: "Eric Steimle" <steimle@xxxxxxxxxxxxx>
> To: <si-list@xxxxxxxxxxxxx>
> Sent: Wednesday, April 14, 2004 2:03 PM
> Subject: [SI-LIST] placement of decoupling caps (again)
>
>
> > I know this has been discussed many times before and so far I have:
> >
> >
> > Read all the Sun papers on the yahoo list
> >
> > Read through many papers from AVX on decoupling
> >
> > Spent some time searching through the list archives
> >
> > And read through many papers suggested in the list archives
> >
> >
> >
> > So far I've come up with a lot of information on how to choose bypass
> > caps, how many to use, what kinds, ESL, ESR, but not much on the correct
> > placement of these bypass caps in a normal system (normal to me would be
> > a processor some ram and maybe some DAAs or other peripherals). While
> > combing through the list archives I've seen some people saying location
> > doesn't matter, while others arguing that it does. So I was hoping that
> > some people could suggest some further sources of information about
> > decoupling cap placement that would help me make more informed
> > decisions.
> >
> >
> >
> > Thanks in advance
> >
> > Eric Steimle
> >
> >
> >
> >
> >
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