[SI-LIST] Re: placement of decoupling caps (again)

The other solution to combat high frequency noise, due to fast switching 
transients, is by continuous ground referencing of all high speed 
signals.  Ground referencing eliminates most of the mode conversion 
noise in via transitions, with ground plane to ground plane vias 
providing the additional shorts necessary to suppress propagation of 
noise throughout the PCB.
If you keep a continuous ground reference on all high speed signals, 
from package to package, then you do not need thin power/ground 
dielectric layers, as Chris Cheng has pointed out many times.

Decoupling capacitors have a maximum effective useful range of 
approximately 100 MHz due to mounted inductance, above that the silicon 
and package are responsible for power delivery.  For 100 MHz and below, 
capacitor placement is relatively unimportment if, and only if, there 
are no appreciable power plane resonances below about 200 MHz.  It is 
when power plane resonances occur that placement of capacitors becomes 
extremely critical, since capacitors can be used to alter the resonance 
pattern with careful placement.  The solution to this problem is to 
eliminate structures which cause mid-frequency (50 to 200 MHz) resonances.

If ground referenced signaling is used, along with power planes without 
mid-frequency resonances, and good capacitor mounting/breakout 
practices, then thin dielectric power/ground layers are not needed, and 
capacitor placement is not critical.

best regards,

scott

Scott McMorrow
Teraspeed Consulting Group LLC
2926 SE Yamhill St.
Portland, OR 97214
(503) 239-5536
http://www.teraspeed.com

Teraspeed is the registered service mark of 
Teraspeed Consulting Group LLC



Lee Ritchey wrote:

>I should have qualified my statement by observing that all of these tests
>have been done with power planes spaced closely together, <10 mils, in
>order to produce a good plane capacitor.  When the planes are far apart,
>  
>
>>15 mils, it is true that one can observe changes in behavior as capacitors
>>    
>>
>are moved about.  Under these conditions, what is also true is that high
>frequency ripple, >200 MHz, is large and doesn't get very good no matter
>what one does with the capacitors.  
>
>As a result, EMI is likely to be high, ripple on Vdd is going to be high
>and the circuit is likely to be "flaky" if there are any wide buses with
>fast rise times.  This problem is fixed by making sure there is a good
>plane capacitor.  This is done by placing the planes close together.  Soon
>as the planes are close together, doesn't matter where you put the caps.
>
>
>Lee W. Ritchey
>Speeding Edge
>P. O. Box 2194
>Glen Ellen, CA 95442
>Phone- 707-568-3983
>FAX-    707-568-3504
>
>I just took the energy it took to be angry and wrote some blues.
>Count Basie
>
>
>  
>
>>[Original Message]
>>From: Lee Ritchey <leeritchey@xxxxxxxxxxxxx>
>>To: Eric Steimle <steimle@xxxxxxxxxxxxx>; <si-list@xxxxxxxxxxxxx>
>>Date: 4/14/2004 3:38:41 PM
>>Subject: RE: [SI-LIST] placement of decoupling caps (again)
>>
>>UMR did a paper in 1995 that determined location is not important as long
>>    
>>
>as you don't cut up the power planes.  Others have repeated those same
>tests, as have I,  and come up with the same answers.
>  
>
>>The proponents of location matters need to do some testing to show that
>>    
>>
>their position is valid.
>  
>
>>Lee
>>
>>Lee W. Ritchey
>>Speeding Edge
>>P. O. Box 2194
>>Glen Ellen, CA 95442
>>Phone- 707-568-3983
>>FAX-    707-568-3504
>>
>>I just took the energy it took to be angry and wrote some blues.
>>Count Basie
>>
>>
>>    
>>
>>>[Original Message]
>>>From: Eric Steimle <steimle@xxxxxxxxxxxxx>
>>>To: <si-list@xxxxxxxxxxxxx>
>>>Date: 4/14/2004 1:59:37 PM
>>>Subject: [SI-LIST] placement of decoupling caps (again)
>>>
>>>I know this has been discussed many times before and so far I have:
>>> 
>>>
>>>Read all the Sun papers on the yahoo list
>>>
>>>Read through many papers from AVX on decoupling
>>>
>>>Spent some time searching through the list archives
>>>
>>>And read through many papers suggested in the list archives
>>>
>>> 
>>>
>>>So far I've come up with a lot of information on how to choose bypass
>>>caps, how many to use, what kinds, ESL, ESR, but not much on the correct
>>>placement of these bypass caps in a normal system (normal to me would be
>>>a processor some ram and maybe some DAAs or other peripherals).  While
>>>combing through the list archives I've seen some people saying location
>>>doesn't matter, while others arguing that it does.  So I was hoping that
>>>some people could suggest some further sources of information about
>>>decoupling cap placement that would help me make more informed
>>>decisions.   
>>>
>>> 
>>>
>>>Thanks in advance
>>>
>>>Eric Steimle
>>>
>>> 
>>>
>>>
>>>
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-- 

Scott McMorrow
Teraspeed Consulting Group LLC
2926 SE Yamhill St.
Portland, OR 97214
(503) 239-5536
http://www.teraspeed.com

Teraspeed(SM) is the service mark of Teraspeed Consulting Group LLC
------------------------



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