[SI-LIST] placement of decoupling caps (again)

I know this has been discussed many times before and so far I have:
 

Read all the Sun papers on the yahoo list

Read through many papers from AVX on decoupling

Spent some time searching through the list archives

And read through many papers suggested in the list archives

 

So far I've come up with a lot of information on how to choose bypass
caps, how many to use, what kinds, ESL, ESR, but not much on the correct
placement of these bypass caps in a normal system (normal to me would be
a processor some ram and maybe some DAAs or other peripherals).  While
combing through the list archives I've seen some people saying location
doesn't matter, while others arguing that it does.  So I was hoping that
some people could suggest some further sources of information about
decoupling cap placement that would help me make more informed
decisions.   

 

Thanks in advance

Eric Steimle

 



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