[SI-LIST] Re: nonlinear in power ground noise of clock driver
- From: Zhangkun <zhang_kun@xxxxxxxxxx>
- To: si-list <si-list@xxxxxxxxxxxxx>
- Date: Fri, 05 Dec 2003 09:22:45 +0800
Dear all:
In order to make the problem clear, I will explain the details:
1.All the model we use in simulation is measured by VNA. Our model is
s-parameter.
2.I simulate in frequency domain by means of impedance curve of caps and
beads.
3.I have simulate the impedance of decoupling circuit. There is only
difference in low frequency domain.
4.There is one PLL in CDC2516. Is this the reason?
I still did not understand why the difference in low frequency could affect the
noise in high frequncy domain.
Best Regards
Zhangkun
2003.12.5
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