[SI-LIST] Re: min/max trace length

Hi
what will happen when the setup margin is negative?

Tmargin = Tcycle - Tclk_to_data_output - Tsetup - Tprop - Tskew - Tjitter

e.g. 100MHz (10ns), setup time 25ns from the flash memory, setup time
controller is 8ns. Is this the right time to add wait states to Tcycle?

best regards
Bernd





2008/8/13 Peterson, James F (EHCOE) <james.f.peterson@xxxxxxxxxxxxx>

> One thing worth noting in the below question and comments. When it comes
> to pcb trace timing, traces can be too long (setup times at the receiver
> are violated, and traces can be too short also (hold times at the
> receiver are violated).
>
> Keep in mind, you can have a clock period of 1Hz and still violate your
> hold time requirements in a conventionally clock circuit.
>
> That is why you have to do the timing analysis. Do it for hold times
> (answer will tell you the minimum trace length), and do it for setup
> times (tells you the maximum trace length).
>
> Regards,
> Jim Peterson
> Honeywell
>
> -----Original Message-----
> From: si-list-bounce@xxxxxxxxxxxxx [mailto:si-list-bounce@xxxxxxxxxxxxx]
>  On Behalf Of steve weir
> Sent: Wednesday, August 13, 2008 5:30 AM
> To: bernd schuster
> Cc: si-list@xxxxxxxxxxxxx
> Subject: [SI-LIST] Re: min/max trace length
>
> Always solve for timing requirements.  Flight time depends on physical
> distance and effective eR.  Stripline traces see the material eR,
> microstrip see a mix of the material and air.  Once you know the fixed
> timng of your chips then you can start to build a budget for flight
> time, and SI effects like loading, ringback, crosstalk induced push-out,
>
> pull-in etc.  At 100MHz SDR you can likely safely tolerate at least 3ns
> flight time which would be at least 17.7".
>
>  From a practical standpoint flash memory timing is so slow that you
> would have to have enormous trace runs before flight time becomes a
> significant issue.
>
> Steve
> bernd schuster wrote:
> > Hi,
> > I often read minimum and maximum trace lengths in datasheets of sdram
> chips
> > (for example). As I figured out the length depends on the setup margin
> and
> > hold margin.
> >
> > If I have a setup margin of 2ns and hold margin of 0.8ns (e.g.)  -
> which
> > formulas will tell me the min. and max. trace length? The system is
> working
> > at 100MHz with a fall time / rise tim of 2ns.
> >
> > How do I have to modify the formula when I want to calculate the
> timing for
> > an external flash memory (without clock traces)?
> >
> > best regards
> > Bernd
> >
> >
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