[SI-LIST] Re: min/max trace length

Bernd,
There are times when a simulator is not strictly necessary, and a good 
spreadsheet timing calculation will do.  Your clock speed suggests you 
may be in the spreadsheet domain.

Build your spreadsheet with provision for every delay variable that you 
can think of.  Some of the delays are not going to be well-specified, 
such as simultaneous switching push-out and crosstalk-induced jitter.  
Include them in your spreadsheet, and make a guesstimate for their 
values.  Zero is probably not the right guess!   As you gain knowledge, 
the guesstimates can be refined, giving you a better picture of your 
real margins.

The setup calculation involves determining the path length from the 
latest data launch to the earliest capture clock.  You find the latest 
common point (usually in the clock distribution) and time from there, 
using min delay in the clock path analysis and max delays in the data 
path analysis.  Forget the data trace length and "margin" for a while.

You should end up with the earliest clock arrival time being later than 
the latest data arrival time, or you are a priori broken.  If not 
broken, the difference in time is the sum of the maximum trace delay 
plus the setup margin.  Allocate as your system and engineering 
judgement allow.

The hold calculation involves determining the earliest launch time and 
shortest data path versus the latest capture clock arrival in the 
launching cycle.  Again, forget the data trace length and margin for a 
while. The data arrival time must be later than the clock arrival or the 
system is potentially broken.  Should the data arrive before the clock, 
the difference is the required minimum trace delay for zero hold 
margin.  Added length provides more hold margin.

The difference between the maximum permissible and required minimum 
trace lengths is available to your board designer as a tolerance on the 
routing length.  Note that you have been calculating in terms of time, 
and the trace delay is a function of Er.  Be sure to talk to your board 
vendor to find out what his process variables are.

Note that when you are calculating the fastest clock in the setup 
spreadsheet, you do not have to use the absolute Min delay from your 
data sheets.  Why?  Because the slowest data paths occur at minimum Vdd 
and max temperature, and the Min specs apply only at Max Vdd and min 
temperature.  The clock (short) path can be calculated at Max delay 
minus a factor for the process variation.  You'll have to research your 
vendors to find out  what that may be.  Similar reasoning applies to the 
calculation of the slow path  in the hold  spreadsheet.

I've used spreadsheets with good results at system speeds considerably 
faster than you are considering.  The big caveat is that SI 
considerations must be met independently of the timing calculation.  
Ringing, or pedestals, on any of your signals must either be eliminated 
by design, or incorporated into your timing spreadsheet.  Net delay is 
not always simply (length * Tpd).  For this, you need a simulator, or a 
well trained sense of intuition in the SI arena.  Complex net topologies 
will blow most people's intuition out of the water, so SI simulation is 
highly recommended.

Regards

Mike
- - - - -
bernd schuster wrote:

>Hi,
>Unfortunately, I`ve no simulation tools... and therefore I read a lot of
>datasheets and application notes from different manufacutres. Their
>recommendation about different trace lengths are very often between 10mm and
>20mm. Maybe that`s the best conditions on the one hand to be routable and on
>the other hand....
>
>What about the skew and jitter calculation? I`m working with an ARM9
>microcontroller with internal sdram controller and an external sdram. Is it
>correct that the clock length have to be as long as the longest databus
>length to get small skew
>
>  
>
>>Of course, if you mean a synchronous interface, you may need a simulation
>>    
>>
>and timing calculation to determine the trace lengths.
>The pcb layout software is able to calculate the normal length of a trace /
>not the manhatten length - but it should be enough
>
>best regards
>Bernd
>
>
>2008/8/13 Benny Yan <zyan@xxxxxxxxxx>
>
>  
>
>>Bernd,
>> Setup and hold margin are the results from the layout length, output delay
>>and input setup and hold time requirements.
>>I think that you mean a source synchronous interface. In this case, the
>>absolute trace lengths are not the main constraint.
>>The setup margin 2ns and hold margin 0.8ns gives you a chance to tune the
>>length matching between clock and data traces.
>>Of course, if you mean a synchronous interface, you may need a simulation
>>and timing calculation to determine the trace lengths.
>>Or simply, you may use 1ns per 6inch to do a rough estimation, but don't
>>forget to reserve enough margin.
>>
>>Benny Yan
>>www.iometh.com
>>
>>-----Original Message-----
>>From: si-list-bounce@xxxxxxxxxxxxx [mailto:si-list-bounce@xxxxxxxxxxxxx]
>>On Behalf Of bernd schuster
>>Sent: Wednesday, August 13, 2008 5:13 PM
>>To: si-list@xxxxxxxxxxxxx
>>Subject: [SI-LIST] min/max trace length
>>
>>Hi,
>>I often read minimum and maximum trace lengths in datasheets of sdram chips
>>(for example). As I figured out the length depends on the setup margin and
>>hold margin.
>>
>>If I have a setup margin of 2ns and hold margin of 0.8ns (e.g.)  - which
>>formulas will tell me the min. and max. trace length? The system is working
>>at 100MHz with a fall time / rise tim of 2ns.
>>
>>How do I have to modify the formula when I want to calculate the timing for
>>an external flash memory (without clock traces)?
>>
>>best regards
>>Bernd
>>
>>
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>>    
>>
>
>
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