[SI-LIST] logic analyzer probes on LVDS

From: evillaf@xxxxxxxxx
To: si-list@xxxxxxxxxxxxx
Date: Tue, 26 Mar 2002 17:13:44 +0000

Gentlemen,

I have a SPI4 bus running at 155 MHz DDR (LVDS) between 
two Xilinx FPGAs that are placed right next to each 
other.  My boss wants to put LA headers on this bus 
(positive signals only).  Any comments?

Thanks in advance.
Ellis
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[SI-LIST] logic analyzer probes on LVDS

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