An example of a transistor with hidden connections to node 0 (unrelated to the present problem because he had no transistors in the simulation): In SPICE, bipolar (NPN, PNP) transistors have four nodes, the fourth (substrate) is optional. If you instantiate only the first three, collector/base/emitter, by default the "substrate" gets connected to node 0. At first, this sounds awful, because many transistors would short-circuit that way (forward bias all the parasitic junctions to the substrate). But I believe the model only has capacitances to that node, no DC representation of those junction diodes. And I don't know if the capacitances in the model are voltage dependent. Regardless, there is a sneak AC path to node 0, unless you specify all four nodes on every BJT in the simulation. I think some of the MOS models have something similar (capacitance that effectively goes to node 0). Andy ------------------------------------------------------------------ To unsubscribe from si-list: si-list-request@xxxxxxxxxxxxx with 'unsubscribe' in the Subject field or to administer your membership from a web page, go to: http://www.freelists.org/webpage/si-list For help: si-list-request@xxxxxxxxxxxxx with 'help' in the Subject field List archives are viewable at: http://www.freelists.org/archives/si-list or at our remote archives: http://groups.yahoo.com/group/si-list/messages Old (prior to June 6, 2001) list archives are viewable at: http://www.qsl.net/wb6tpu