[SI-LIST] junior designer question

Dear experts,
For my design I need to connected several memories with a virtex (FPGA)
I have the following memories:
10xSRAM CY7C1069AV33
5xSDRAM MT48LC16M16
1xFLASH AM29LV017D
1xPROM SMJ27C010
All memories are sharing the same address bus.

Can you tell me how i can determine if i need to use a address buffer?
What are the characteristics that are importent?
I you have documents of application notes that describe how to determine the
need of a buffer, please let me know.

I'm thinking to use the 54LVTH16244A of TI, but i need to calculate that
this driver is OK for my design.

Please let me know if you can help me.

Best regards,
Nico

Nico Fleurinck
Junior Design Engineer
VERHAERT Satellites & Platforms
Hogenakkerhoekstraat 21
B-9150 Kruibeke

Tel : +32 3 250.1984
Fax : +32 3 254.1008
e-mail : nico.fleurinck@xxxxxxxxxxxx
Visit us : www.verhaert.com



------------------------------------------------------------------
To unsubscribe from si-list:
si-list-request@xxxxxxxxxxxxx with 'unsubscribe' in the Subject field

or to administer your membership from a web page, go to:
http://www.freelists.org/webpage/si-list

For help:
si-list-request@xxxxxxxxxxxxx with 'help' in the Subject field

List archives are viewable at:     
                http://www.freelists.org/archives/si-list
or at our remote archives:
                http://groups.yahoo.com/group/si-list/messages 
Old (prior to June 6, 2001) list archives are viewable at:
                http://www.qsl.net/wb6tpu

Other related posts: