[SI-LIST] Re: internal time step too small error in transient analysis

Boli-
I have on rare occasion found an RC combination in my path that was very small 
which seemed to be related to the internal time step error.  Check to see if 
this might be your case if so try a slight modification to one or both values 
which in my case(s) cleared the error when running Hspice versions from 
2000-2007.
-Jory

----- Original Message ----
From: Ray Anderson <ray.anderson@xxxxxxxxxx>
To: si-list@xxxxxxxxxxxxx
Cc: bolisudha@xxxxxxxxx; Ray Anderson <raya@xxxxxxxxxx>
Sent: Wednesday, December 19, 2007 9:16:39 AM
Subject: [SI-LIST] Re: internal time step too small error in transient analysis

 Boli-

I don't know if I can help specifically, but here are a few comments:

It looks like the "time step too small" fixes you found during your
Google search are Spice specific. While the transient solver engine
within ADS is similar in many respects to Spice many of the details are
different. Particularly with respect to the various parameters you can
adjust that affect the transient simulation.

Have you checked on the Agilent support web pages
(https://edasupportweb.soco.agilent.com) for info on this issue? There
are a number of documents there that address this particular issue as  it
applies to ADS.

Also, I notice you are using ADS2004A. A lot of improvements have gone
into the tool since that release. The current release is ADS2006 update
3 and the new 2008 release is due out next month. If at all possible  I'd
see about upgrading to the latest and greatest.


Have you contacted Agilent support yet on this issue? Their support
engineers are usually quite adept at solving this sort of problem as
they've probably fielded similar problems from other users thousands of
times.

Best Regards,

-Ray

Raymond Anderson
Senior Signal Integrity Staff Engineer
Advanced Platforms Group
Advanced Products Division
Product Technology Department
Package Design Engineering
Xilinx Inc.
2100 Logic Drive
San Jose, California  95124
(408) 626-6277


> -----Original Message-----
> From: si-list-bounce@xxxxxxxxxxxxx
[mailto:si-list-bounce@xxxxxxxxxxxxx]
> On Behalf Of boli sudha
> Sent: Tuesday, December 18, 2007 10:57 PM
> To: si-list@xxxxxxxxxxxxx
> Subject: [SI-LIST] internal time step too small error in transient
> analysis
>=20
> hi all,
>          iam doing a project on WLAN synthesizer.iam using ADS 2004A.
i
> have
> designed individual blocks of VCO,divider blocks. for divider iam
using
> master slave flipflops. so initially i need to reset them, for that i
used
> a
> reset signal. if i run this  divider block it is running individually
in
> transient analysis. but if i integrate this block with VCO's output  it
is
> giving internal time step error.  so i changed every  thing like  below
> which
> i got when i search  in google. but error is coming again .
>=20
> 1. Increase rise-time and/or fall time of the pulse
> 2. Increase ITL4 between 25 and 500, (default is 10)
> 3. Change TRAP method to GEAR
> 4. Change MAXORD to 3, 4, 5, and 6
> 5. Change TRTOL to 25 (default is 7)
> 6. Change LVLTIM from 2 to 1
> 7. Increase TNUM
> 8. Change ITL4 to 100
> 9. Reset above, and set these
> RELTOL =3D 0.01
> ABSTOL =3D 1.0e-9
> VNTOL =3D 1.0e-4
> LVLTIM =3D 1
> METHOD =3D GEAR
> MAXORD =3D 2
> TNUM =3D "pick big number"
> ITL4 =3D 100
>=20
> can anybody help me please.
>=20
>=20
>=20
>=20


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