[SI-LIST] internal time step too small error in transient analysis
- From: "boli sudha" <bolisudha@xxxxxxxxx>
- To: si-list@xxxxxxxxxxxxx
- Date: Wed, 19 Dec 2007 12:27:19 +0530
hi all,
iam doing a project on WLAN synthesizer.iam using ADS 2004A. i have
designed individual blocks of VCO,divider blocks. for divider iam using
master slave flipflops. so initially i need to reset them, for that i used a
reset signal. if i run this divider block it is running individually in
transient analysis. but if i integrate this block with VCO's output it is
giving internal time step error. so i changed every thing like below which
i got when i search in google. but error is coming again .
1. Increase rise-time and/or fall time of the pulse
2. Increase ITL4 between 25 and 500, (default is 10)
3. Change TRAP method to GEAR
4. Change MAXORD to 3, 4, 5, and 6
5. Change TRTOL to 25 (default is 7)
6. Change LVLTIM from 2 to 1
7. Increase TNUM
8. Change ITL4 to 100
9. Reset above, and set these
RELTOL = 0.01
ABSTOL = 1.0e-9
VNTOL = 1.0e-4
LVLTIM = 1
METHOD = GEAR
MAXORD = 2
TNUM = "pick big number"
ITL4 = 100
can anybody help me please.
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