[SI-LIST] Re: impedance controlled vias

Quazi,
designing via structures from scratch with very good impedance controls is 
one of the more difficult tasks in board design. Closed formulas and even 
simple simulators will only get you so far; ultimately you will either 
need a good 3D field solver, or go through a few iterations of a small 
test PCB. Ideally both - first simulate and then measure. 

That said, you can often get at least reasonable performance with some 
simple tools. Forget the formulas from the Black magic book, especially 
the inductance formula is not usable (it assumes a very specific distance 
to the ground return via). Howard Johnson has a few later articles on his 
website that provide much better information. And in the book he already 
cautions that the C and L numbers yield orders of magnitude, but no 
anything resembling an accurate result.

Pseudo-coaxial via arrangements are one of the most straightforward 
approaches if you have freedom in the return via placement, which you say 
haven't. But keep in mind that not only ground vias count as return vias, 
but -assuming good power decoupling - also power vias, Maybe that fact 
already improves your situation (I assume there are about as many power 
vias as ground vias in your BGA pinout).

There are closed formulas for such pseudo-caxial structures (look at 
Johnson's "High Speed Signal Propagation" book for examples). To match 
reality to that model, you'll need to remove the ground and power planes 
from inside the structure, which may not be such a good idea underneath 
the BGA since many such cutouts together can create large plane-less 
openings below the BGA.  Also you want to avoid stubs, i.e. use blind vias 
by backdrilling or sequential lamination, to further simplify the 
structure (simplyfy for simulation; manufacturing effort and cost will fo 
course go up).

In addition to closed formulas, you can also build an approximate model 
using a simple 2D fiel solver (e.g. TNT/MMTL,freely available from 
Sourceforge, google for "TNT field solver"). Approximate the vias by 
cylindrical conductors. This works reasonably well when there are no 
ground or power planes inbetween the vias (meaning thos planes have 
cutouts) and there are no stubs.

From my experience, given typical via dimensions and spacings, most of the 
time you fight excess capacitance rather than excess inductance. If that 
is your case, removing the via stubs, minimizing the via diameters (this 
requires small board thickness), maximizing the plane cutout size (within 
the constraint that you don't want the cutouts run into each other) are 
possible remedies.

IMHO anything beyond those first-order models is really only possible with 
a 3D solver.

Wolfgang







"qazi" <qazi@xxxxxxxxxx> 
Sent by: si-list-bounce@xxxxxxxxxxxxx
02/20/2009 01:45 PM

To
<si-list@xxxxxxxxxxxxx>
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Subject
[SI-LIST] impedance controlled vias






Guys,
Is there any good literature on impedance controlled vias? All I could 
find
is the EDN paper by Thomas Neu (http://www.edn.com/article/CA324403.html).
This calls for a signal via surrounded by 4 Gnd Vias, which is impossible
for my .5mm BGA I/O pins. Also the L and C equations shows inverse
coshyperbolic function with D/2a as argument, that's <1 and can't be true.

If anyone has some sort of formula to measure via impedances on a non 
ideal
case, something that will take into account of the following, would be
really helpful:

a) TH signal via on a 8 layer board with 2/3 GNd planes. 
b) Gnd Vias for return path are somewhat further away from the IO pins.
c) power planes surrounding the via should add some extra capacitance as I
can't have huge antipad.
d) no via Stub.

My one is a thin board .040" and vias are .006" in dia.

I have Howard Johnson black magic, I have seen the equations on L and C of
the vias on page 257-258. Not sure how these would come close in real life
to measure impedance.
-Qazi




-----Original Message-----
From: si-list-bounce@xxxxxxxxxxxxx [mailto:si-list-bounce@xxxxxxxxxxxxx] 
On
Behalf Of steve weir
Sent: Thursday, February 19, 2009 7:46 AM
To: Avtaar Singh
Cc: si-list@xxxxxxxxxxxxx
Subject: [SI-LIST] Re: Current Mode Compensation for DC/DC Buck Regulators

There are lots of books out there.  Pressman comes to mind, but there 
are many others.  Virtually all of the SMPS controller / regulator 
manufacturers have many app notes on current mode buck converters built 
with their parts. 

Steve
Avtaar Singh wrote:
> Gurus:
> Can you kindly name some best reads (books / IEEE papers / white papers
> etc.) on Current Mode Compensation for DC/DC Buck Regulators (in 
details)
> for beginner designers?
>
> Regards,
> Avtaar Singh
>
>
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