[SI-LIST] Re: impedance controlled vias

Guys,
Is there any good literature on impedance controlled vias? All I could find
is the EDN paper by Thomas Neu
(http://www.edn.com/article/CA324403.html).This calls for a signal via
surrounded by 4 Gnd Vias, which is impossible for my .5mm BGA I/O pins. Also
the L and C equations shows inverse coshyperbolic function with D/2a as
argument, that's <1 and can't be true.

If anyone has some sort of formula to measure via impedances on a non ideal
case, something that will take into account of the following, would be
really helpful:

a) TH signal via on a 8 layer board with 2/3 GNd planes. 
b) Gnd Vias for return path are somewhat further away from the IO pins.
c) power planes surrounding the via should add some extra capacitance as I
can't have huge antipad.
d) no via Stub.

My one is a thin board .040" and vias are .006" in dia.

I have Howard Johnson black magic, I have seen the equations on L and C of
the vias on page 257-258. Not sure how these would come close in real life
to measure impedance.


-Qazi
PS: My earlier mail showed only 1st line. Not sure how this might happen.




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