[SI-LIST] Re: how to evaluate the lead inductance of chip packages

Lee, David clarified to me that he was trying to understand the basis for 
fixed L numbers in an IBIS model.  So in his circumstance, the assumption 
was that all of the elements were small enough to treat each as lumped.

Steve.
At 09:18 AM 12/21/2005 -0800, Lee Ritchey wrote:
>This whole explanation ignores the distributed capacitance along the length
>of the lead.  This is not a good thing to do for very fast signals.
>
>Lee W. Ritchey
>Speeding Edge
>P. O. Box 2194
>Glen Ellen, CA 95442
>Phone- 707-568-3983
>FAX-    707-568-3504
>
>I just used the energy it took to be angry to write some blues.
>Count Basie
>
>
> > [Original Message]
> > From: david <zhao.dave@xxxxxxxxx>
> > To: <si-list@xxxxxxxxxxxxx>
> > Date: 12/20/2005 5:46:46 PM
> > Subject: [SI-LIST] how to evaluate the lead inductance of chip packages
> >
> > Dear sir,
> >        Whenever we analyzed the inductance of a circuit, we have to
>consider
> > the loop. Whatever mutual inductance or self-inductance were mentioned, we
> > all need to calculate the area of the loop that was constructed by the
> > forward signal line and the back power plane. That was easy to be
> > comprehended, in terms of the concept of induction, we had to
> > understand that the change of flux led to the loop current. And in this
> > situation, the inductance distributed in the loop nearly uniformly. But
> > most time, we extracted the lead inductance out of the integrated value of
> > the loop, and considered it separately. It seemed that the lead had a
> > inherent inductance which wasn't related to the area of the loop. But I
> > couldn't comprehended how a straight wire, other than loop, could possess
> > the inductance. No area No flux.
> > Thanks a lot.
> >
> > --
> > BEST WISHES
> >
> > Joey.zhao
> >
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