[SI-LIST] ground planes at top / bottom layer

Hi,
I`ve one small question about the usage of ground planes at the top and
bottom layer. I thought it would be great to use them, but the atmel
evaluation boards (for example) do not use an ground plane on the top layer
or bottom layer. They use for example an 8 layer stack design (where layer 5
is a vcc plane and layer 2 is a ground plane).

Are there any disadvantages of using ground planes at the top / bottom
layer? In my first 4-layer board I use ground planes at the top, bottom and
at the second layer. I connect them with a lot of vias.


best regards
Bernd


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