[SI-LIST] Re: f vs. Tf vs. jitter

Steven and all,
Two points I want to refresh here since I remember the mail about PLL
locking time constant wrt jitter etc in optical SERDES standard (if I recall
correctly).

- There is a very long time constant jitter in optical domain due to chirp
(chirp=instantaneous frequency (or wavelength) changes). Especially, thermal
chirp (laser diode characteristics) gives very longer time constant
impairment than adiabatic chirp. In my past experience using my in-house
built chirp meter, I found few hundreds nanoseconds time constant easily. I
guess these days it is easier to control than before. Sometimes in SERDES
standard, they put this long time constant just simply because "want-to-be
safe".

-  Multiple orders difference in locking: We know that locking in time axis
is closely related to slew rate in analog domain. Same principle also
applies in digital counters which is only a cascaded dF/Fs. In dF/F the
logic threshold determine the time point to switch the logic state. Having
said that, if cascaded logic chain is implemented monolithically, a set of
logic thresholds in a chain is well localized. This gives you such a nice
locking results across the orders. I would say this scheme is good because
something that related to photonics I would stick to broadband (in this
case, ironically, 'broadband' means 'digital' because "logic state" is time
invariant unless it changes meaning '0'Hz min frequency and maximum of its
toggling frequency)

Hope this help.

Kihong Joshua



On 6/19/07, steve weir <weirsi@xxxxxxxxxx> wrote:
>
> Andy, in a PLL the stability of the VCO, as well as noise and leakage in
> the phase comparator and error amplifier plays directly to jitter.
> Those all get magnified by the phase comparator interval compared to the
> nominal VCO interval in a digital, or traditional mixed analog / digital
> PLL.  In a pure analog PLL using multipliers there is still the issue of
> multiplier linearity and noise.  This was somewhat central to Chris
> Cheng's objection to the huge ratio between VCO operating frequency and
> phase comparator interval for certain signaling standards.  That tall
> ratio belabors the analog electronics with greater stability and noise
> sensitivity than would be necessary with a shorter ratio.
>
> Best Regards,
>
>
> Steve.
> Andrew Ingraham wrote:
> > Steven,
> >
> > "Analog frequency synthesis techniques" includes a PLL, even with
> digital
> > counters and dividers in it.  (As opposed to direct digital frequency
> > synthesis.)
> >
> > As such, analog frequency synthesizers can be easily programmed for
> > different division ratios and operating frequencies, especially as far
> as
> > the output is concerned.  And they do not necessarily have the problem
> with
> > slew rate when generating low-frequency events.
> >
> > There are also analog based synthesis techniques that don't use digital
> > counters and such, only analog circuits (though some are nonlinear,
> > frequency multipliers and such).  But these are less common.
> >
> > If you are talking about a need to generate sine waves, then yes there
> is a
> > link between frequency and slew rate OF THAT OUTPUT SIGNAL.  But that is
> > because of the desired output waveform, not the method of frequency
> > synthesis.
> >
> > But if you have a need to trigger something downstream, then a sine wave
> > output is potentially a poor choice, especially if there is a need for
> wide
> > frequency ranges and/or very low-frequency events.
> >
> > In your situation I'd be tempted to stay with digital counters to get
> from
> > 80MHz to 10Hz, as opposed to a PLL unless I needed an odd ratio or
> > something.  If phase tweaking is necessary, the presence of 80MHz ought
> to
> > give them the ability to minimize the amount of analog delay adjustment
> that
> > is necessary.
> >
> > Yes, it's true that electronic (analog) delay lines generate lots of
> jitter
> > and that it increases with their delay time.
> >
> > NIST has a number of references (such as the Time and Frequency User's
> > Manual, which I think they now have on-line) that talk about things like
> > locked lasers, in a little bit of detail that might give you some hints
> > about how it's done.
> >
> > Seven orders of magnitude isn't necessarily an issue; I mean it's not
> like
> > trying to make a PLL itself operate over 7 orders of magnitude, or a
> linear
> > RF amp over a similar amplitude range.  If you think of it as a weak
> loop
> > where the second oscillator (laser) is mostly free-running and has low
> > jitter, and just needs occasional updates to tweak its phase, then it's
> not
> > so bad.  There are trade-offs and limitations (won't work if the second
> osc.
> > wanders too much), but if these are managed, 7 orders of magnitude is
> not
> > necessarily a problem.
> >
> > Keep in mind ... if you will be talking to a room full of PhDs, they
> will
> > probably take over the conversation anyway and steer it where they want
> it
> > to go, and you can't help but be made to feel like a fool.  Just don't
> sweat
> > it.
> >
> > Regards,
> > Andy
> >
> >
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