# [SI-LIST] Re: eye diagram

• From: "San Miguel, Shane" <shane.san.miguel@xxxxxxxxx>
• To: <kbagga31@xxxxxxxxx>, <si-list@xxxxxxxxxxxxx>
• Date: Mon, 29 Sep 2003 08:40:31 -0700

```An eye diagram shows you how sloppy you can be :) =20

The "eye" is the boundary that a signal may vary in amplitude and time =
with reference to another signal while maintaining a passing test =
condition.  If a signal is supposed to be aligned with clock, it has a =
spec that says it can vary +- some given time amount (can be thought of =
as something like jitter) around this reference and still be valid.  The =
voltage level that this signal rides at (usually Vtt or Vref) can also =
vary a +- amount around it's level.  If you combine the +- voltage =
variance and the +- time variance you end up with something the shape of =
an eye.  In the broadest generalization, the more "eye" you have, the =
more margin-to-fail you have.

The example I give is using spec values but in practice, you vary the =
voltage and timing to push the device until failure thus defining the =
eye.

Shane San Miguel=20
Senior Product Engineer=20
Platform Memory Operations=20
Intel Corporation=20
=20

-----Original Message-----
From: si-list-bounce@xxxxxxxxxxxxx
[mailto:si-list-bounce@xxxxxxxxxxxxx]On Behalf Of karan bagga
Sent: Monday, September 29, 2003 1:37 AM
To: si-list@xxxxxxxxxxxxx
Subject: [SI-LIST] eye diagram

Hi,
=20
Want to know about eye diagram.
How does eye diagram plays a role in desiging Multi Gigaherts PCBs ?
What is the methodology i.e do eye diagrams come in datasheets.
Need some basic understanding on relation with eye diagram and SI.
=20
Regards
Karan

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