[SI-LIST] Re: effect of termination on slew rate
- From: "Vishnu Mohan" <vishyin8@xxxxxxxxx>
- To: Bill.Cohen@xxxxxxxxxxxxxxxx
- Date: Wed, 15 Mar 2006 11:25:29 +0530
Dear Nidhir,
What ever you have mentioned is *end termination*.
It is not necessary that the resistor should be connected to Supply, it can
be connected to GND too. But the main reson for connecting the to supply is
for driving the signal.
For any AC signal analysis you can consider th DC supply as GND. The
parallel termination will be reducing the rice time delay compared to the
series termination as the time constant is ZoC/2.
On 3/14/06, Bill.Cohen@xxxxxxxxxxxxxxxx <Bill.Cohen@xxxxxxxxxxxxxxxx> wrote:
>
> Nidhir,
>
> The GDDR3 driver is actually a POD (pseudo open drain) driver. There is a
> device to pull down (40 ohms) and a device to pull-up (60 ohms). It is
> weaker than the 40 ohm pull down device but it is there to help the 60 ohm
> resistor at the far end pull up the signal line.
>
> --------------------------------------------------------------
> | Bill Cohen
> | Toshiba America Electronic Components
> | Mixed Signal Design Group
> --------------------------------------------------------------
>
>
>
> "Nidhir Kumar"
> <nidhir.kumar@gma
> il.com> To
> Sent by: si-list@xxxxxxxxxxxxx
> si-list-bounce@fr cc
> eelists.org
> Subject
> [SI-LIST] effect of termination on
> 03/13/2006 03:12 slew rate
> PM
>
>
> Please respond to
> nidhir.kumar@gmai
> l.com
>
>
>
>
>
>
> Dear Gurus
>
> I am designing graphical DDR3 driver which has 40 ohm
> push-pull driver and 60 ohm termination (ODT) to the
> VDDQ at the far end. Since the termination is to the
> supply, I would assume that rise slew at the far end
> should be higher. But rise and fall slews looks very
> symmetrical in the HSPICE simulations.
>
> Can someone please explain me the theory behind this
> phenomenon. I read somewhere that DC terminations
> don't affect AC behavior. But I find it difficult to
> digest. Any thoughts?
>
> Thanks,
> Nidhir
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