[SI-LIST] Re: digital to analogue noise coupling

Steve:

Thanks for your suggestions. Actually all the circuits here are +5V. Will do
some more measurement as you suggested to confirm the coupling channel.

Regards

Perry


=======================================

Perry Qu

Design & Qualification, Alcatel Canada

600 March Road, Ottawa ON, K2K 2E6

DID: 613-7846720    Fax: 613-5993642

Email: perry.qu@xxxxxxxxxxx

=======================================


-----Original Message-----
From: steve weir [mailto:weirsi@xxxxxxxxxx] 
Sent: Monday, June 20, 2005 10:18 AM
To: Perry Qu; 'si-list'
Subject: RE: [SI-LIST] digital to analogue noise coupling

Perry, I assume that none of the voltages here are above 3V.  So you have 
about 2% coupling   If your scope can do a good difference, probe the 
ground plane on either side of the analog section.    That will tell you if 
the image is just lifting one portion of the analog circuity or another.  If
the coupling is capacitive even a few pf looking into 100K will hold-up for
244ns.  Just to test, scale the impedances down in your analog circuit and
see if that substantially alters the crosstalk.

Steve.
At 09:47 AM 6/20/2005 -0400, Perry Qu wrote:
>Thanks, steve. The crosstalk is in the range of 60 mV. The return path 
>of the clock is a solid plane and the clock is routed on either side of 
>the plane. There are about total 12 drops on 2 branches of the clock 
>(series terminated at both branches). The stackup looks like:
>
>Component (short analogue/digital breakout)
>Sig2 (most of analogue routing)
>Sig3 (clock)
>Gnd
>Sig4 (clock)
>...
>
>As I understood, there is some capacitive coupling as clock on sig3 
>pass underneath component pads on component side. Also, some inductive 
>coupling is bound to happen as analogue routing on sig2 which is far 
>away from the plane will see noise induced from the clock loop 
>(sig2/gnd) -- this is small as most of the analogue traces on sig2 are 
>routed perpendicular to sig3, and there is only a few routed at an 45 
>degree angle.  However, even with all these capacitive/inductive 
>coupling, it still does not explain why I see the copy of the clock 
>rather than glitch corresponding to rising/falling edges only.
>
>Regards
>
>Perry
>
>=======================================
>
>Perry Qu
>
>Design & Qualification, Alcatel Canada
>
>600 March Road, Ottawa ON, K2K 2E6
>
>DID: 613-7846720    Fax: 613-5993642
>
>Email: perry.qu@xxxxxxxxxxx
>
>=======================================
>
>
>-----Original Message-----
>From: steve weir [mailto:weirsi@xxxxxxxxxx]
>Sent: Monday, June 20, 2005 9:03 AM
>To: Perry.Qu@xxxxxxxxxxx; si-list
>Subject: Re: [SI-LIST] digital to analogue noise coupling
>
>Perry, how much crosstalk are we talking about?
>
>A couple of things to consider:  Planes don't provide effective 
>magnetic shielding to low frequency interference.  Your amplifier nodes 
>are likely a pretty high impedance making a net TC well above the 244ns 
>half period of your CODEC clock.  What does the return path for that 
>clock look like?  How much drop in the path does the clock induce?  And 
>is that the image that you are seeing?
>
>Steve.
>
>At 08:45 AM 6/20/2005 -0400, Perry Qu wrote:
> >Good morning,
> >
> >I was asked to help troubleshoot a digital-to-analogue noise coupling 
> >issue on a design. There is a 2MHz clock routed underneath an 
> >analogue circuitry and we picked up a copy of the 2 MHz clock with 
> >much smaller amplitude -- small for digital but large enough to 
> >interfere with analogue
>circuit.
> >
> >The exact same copy of analogue circuitry with no clocks routed 
> >underneath works fine.
> >
> >Checked the layout of the mal-functioning circuitry, I found that 
> >there is small capacitive coupling -- only happened  where the clock 
> >routed underneath some analogue components pads; Inductive coupling 
> >is also small as most of the analogue circuit are routed either 
> >perpendicular or at an angle to the digital traces.
> >
> >The most puzzling part is that the crosstalk noise repeat the source
clock.
> >This seems to suggest that this is neither capacitive nor inductive 
> >coupling as those will induce noise at rising or falling edge only, 
> >not at the DC portion. It looks like there is some DC link between 
> >the digital and analogue but could not locate that from schematics or 
> >layout. Also,  the circuit with no clock routed underneath works fine.
> >
> >Any thoughts ?
> >
> >Thanks
> >
> >Perry
> >
> >=======================================
> >Perry Qu
> >
> >Design & Qualification, Alcatel Canada
> >
> >600 March Road, Ottawa ON, K2K 2E6
> >
> >DID: 613-7846720    Fax: 613-5993642
> >
> >Email: perry.qu@xxxxxxxxxxx
> >
> >=======================================
> >
> >
> >
> >
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