[SI-LIST] Re: digital circuits radiated emission as a function of VDD
- From: "Curt McNamara" <CurtM@xxxxxxxxxxx>
- To: <junfeng.zhou@xxxxxxxxx>, <a.ingraham@xxxxxxxx>
- Date: Mon, 2 Jul 2007 17:56:53 -0500
EMC engineers (who actually live on another list) sometimes use the
following "rules of thumb" for emissions situations:
Broadband noise (i.e. wide spectrum) often comes from common mode
voltages with a (physically) large return path (i.e. undefined or
unintentional). Since the return path is a function of parasitic
elements it is likely not in your model. Given that common mode currents
are small, there has been discussion that logic families with lower
voltage swings would produce less emissions. There are likely papers
about this in past IEEE EMC Society Conference Proceedings.
Narrowband noise (i.e. an emission peak limited in bandwidth) often
comes from current flowing in a loop. An example would be a clock trace,
perhaps poorly terminated. Since load current tends to be small (uA?),
it may not have a strong relation to voltage swing. It is possible a
model based on emissions from loop current would not show increased
emissions from a higher voltage swing, since the change in trace current
is small. It does turn out correctly terminating the clock (which may
mean increasing the current in the trace) tends to decrease emissions.=20
Also please note I am talking about the swing from Voh to Vol (i.e.
signaling levels).
Curt
Curt McNamara // senior electrical engineer=20
Logic Product Development
411 Washington Ave. N. Suite 400
Minneapolis, MN 55401
T // 612.436.5178
F // 612.672.9489
www.logicpd.com=20
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-----Original Message-----
From: si-list-bounce@xxxxxxxxxxxxx [mailto:si-list-bounce@xxxxxxxxxxxxx]
On Behalf Of jun feng
Sent: Monday, July 02, 2007 3:28 AM
To: a.ingraham@xxxxxxxx
Cc: si-list
Subject: [SI-LIST] Re: digital circuits radiated emission as a function
of VDD
Hello Andy,
I do mean the first situation.
In my measurements, the core circuit size, the input data and the
clock frequency are fixed, the only parameter I play is VDD. If I plot
PSD of power supply current
in dBuV (X axis is frequency, in log scale), then the relationship
is perfectly linear. Is that right, reasonable ? are there any theory
on this ?
regards,
Junfeng
On 6/29/07, Andrew Ingraham <a.ingraham@xxxxxxxx> wrote:
>
> > Generally speaking , what is the relationship between the digital
> > circuits radiated emission( peak emission or maybe RMS ?) and the
> supply
> > voltage ? I could not find an exact answer for this. Maybe you guys=20
> > here can educate me ! Thanks,
>
> This is a pretty open question. Perhaps you could clarify.
>
> Do you mean, given a fixed circuit, how do radiated emissions vary as=20
> we vary the supply voltage? (Generally speaking, higher Vdd means=20
> higher currents, and tends to cause faster switching times, both of=20
> which will lead to greater emissions.)
>
> Or do you mean something like the following: As supply voltages have=20
> decreased over the years, what is the relationship between radiated=20
> emissions and the nominal Vdd?
>
> Or in a more specific case, if we were to do 'ideal' scaling applied=20
> to CMOS (where all parameters scale in step with one another according
> to certain defined relationships) how to radiated emissions vary with=20
> that scaling?
>
> The latter two are not easily answered. I'm guessing you mean the=20
> first.
>
> Regards,
> Andy
>
>
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