[SI-LIST] Re: digital circuits radiated emission as a function of VDD
- From: "jun feng" <junfeng.zhou@xxxxxxxxx>
- To: a.ingraham@xxxxxxxx
- Date: Mon, 2 Jul 2007 10:27:48 +0200
Hello Andy,
I do mean the first situation.
In my measurements, the core circuit size, the input data and the clock
frequency are fixed, the only parameter I play is VDD. If I plot PSD of
power supply current
in dBuV (X axis is frequency, in log scale), then the relationship is
perfectly linear. Is that right, reasonable ? are there any theory on this
?
regards,
Junfeng
On 6/29/07, Andrew Ingraham <a.ingraham@xxxxxxxx> wrote:
>
> > Generally speaking , what is the relationship between the digital
> > circuits radiated emission( peak emission or maybe RMS ?) and the
> supply
> > voltage ? I could not find an exact answer for this. Maybe you guys here
> > can
> > educate me ! Thanks,
>
> This is a pretty open question. Perhaps you could clarify.
>
> Do you mean, given a fixed circuit, how do radiated emissions vary as we
> vary the supply voltage? (Generally speaking, higher Vdd means higher
> currents, and tends to cause faster switching times, both of which will
> lead
> to greater emissions.)
>
> Or do you mean something like the following: As supply voltages have
> decreased over the years, what is the relationship between radiated
> emissions and the nominal Vdd?
>
> Or in a more specific case, if we were to do 'ideal' scaling applied to
> CMOS
> (where all parameters scale in step with one another according to certain
> defined relationships) how to radiated emissions vary with that scaling?
>
> The latter two are not easily answered. I'm guessing you mean the first.
>
> Regards,
> Andy
>
>
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