[SI-LIST] differential pair routing topology

Hi SI Experts,

I'm hoping to get some informal opinion about differential pair routing. 
I'm looking at a board with some 100 ohm differential pairs, both video 
LVDS and DDR clock lines, implemented as stripline.

1) I'm considering the routing topology. Density is a factor, space for 
routing channels is limited. For width / clearance rules I could use, 
say, 4/8/4 (mils). I think this could be considered "loosely coupled". 
This could be routed using a 12 (or divisor of) mil grid. But this 
spacing can not be maintained the entire length, it must vary slightly 
at the IC and connector fanouts / vias. So the question is, would it be 
better to increase the spacing to maintain a more consistent impedance 
profile, or does it not make a significant difference?

2) I understand the primary reason for not using 90 degree corners is 
the impedance discontinuity due to the capacitance of the extra corner 
area, so it is better to use 45 degree corners. Then, the routing grid 
has to support ~0.4 of the space to maintain the proper gap in the 
diagonal sections. So the question is, how bad are 90 degree corners for 
differential pairs, should they be routed entirely with 45 degree corners?

I know that every case is different and there are many variables. I'm 
not asking anyone to run simulations for me or anything like that, just 
looking for casual comments.

Thanks,

Ivor Bowden
Engineer
Curtiss-Wright Controls
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