[SI-LIST] Re: diff pair signal
- From: "Landrum, Chris" <chris_landrum@xxxxxxxxxx>
- To: <gopalak@xxxxxxxxxxx>, <si-list@xxxxxxxxxxxxx>
- Date: Wed, 30 Jun 2004 11:34:58 -0400
I recall an instance where a design was using a high speed (156MHz) PECL
oscillator to drive a 1.8V CMOS SE clock input. The positive leg was
AC-Coupled and then biased to suit the clock input. The negative leg
was pulled to logic GND.
This was done for the simple reason that oscillators don't typically
have 1.8V outputs... A translator is just another expense. It worked
well enough.
Chris Landrum
PCBA Design Engineer
Maxtor Corporation
-----Original Message-----
From: si-list-bounce@xxxxxxxxxxxxx [mailto:si-list-bounce@xxxxxxxxxxxxx]
On Behalf Of Gopalakrishnan Sethuraj
Sent: Wednesday, June 30, 2004 10:09 AM
To: si-list@xxxxxxxxxxxxx
Subject: [SI-LIST] diff pair signal=20
Hello=20
=20
Is there any scenario where one (positive) of the differential pair
signal output will be connected to single pin in LVDS or other logical
interfaces ?
=20
=20
Thanks&Regards
Gopalakrishnan=20
=20
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=20
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