[SI-LIST] Re: current return-path for differential pair on PCB

Hi Istvan,

You are correct.  And there are other factors which make your judgment 
more appropriate.  For multiple conductor transmission lines the 
characteristic impedance and the terminations are matrices and vectors.  
For SATA, the differential pairs are "lightly coupled" meaning that the 
impedance line to line is high--for a SATA cable it is 60 ohms each side 
to ground and 600 ohms line to line.  This is close to the reference 
termination of 50 ohms each side to ground and infinite line to line.  
Mismatches in transmission lines lead to reflections and this occurs in 
the common mode as well.  The SATA connector has a fairly high common 
mode mismatch (because some folks said CM doesn't matter) and when 
combined with other common mode mismatches, a common mode resonance 
appears.  Resonant effects magnify noise and imbalanced signals. 

The usual approach to common mode noise is to try to get high mode 
isolation, that is, good impedance balance (matching skew through trace 
lengths).  This is indirect since it doesn't help CM noise. 

Another item of note is in PCB configurations, only those that have 
broadside coupled lines can achieve "tightly coupled" lines, that is, 
low impedance line to line.  Hence, "lightly coupled" is a common PCB 
implementation.

EMI is a consideration that is directly related to the CM noise.  This 
is the reason behind the restrictive specifications on rise/fall time 
matching and skew.  The CM conditions are those that create the EM 
fields responsible for emission (and susceptability as well).

The other consideration that is often neglected is the limited dynamic 
range that transmitters and receivers possess.  When extraneous signals 
such as noise and reflections are impressed onto a transmitter output or 
a receiver input it is possible to drive these into a bias condition 
beyond design limits where it functions differently.  All electronic 
outputs and inputs have a limited voltage range.

This topic is one of those where an understanding of how systems work 
and fail is key to setting up tests that expose the defect.  Many 
implementors fail to understand limitations and do not create tests that 
create failure conditions, effectively testing only the typical cases. 

Regards,
Chuck Hill, SATAIO Phy WG Chair
 

Istvan Nagy wrote:
> hi
> for a differential pair, like PCIe or SATA, some people (some of my 
> colleagues) say, its not needed to have a continous good current return path 
> since the differential voltage is referenced only to the other signal-trace 
> in the pair.
>
> I think the current return path has to be continous even for diffpairs, 
> because:
> 1.) Common mode noise:
> if the return path is not continous, then it creates loops for the common 
> mode noise, so the common mode noise will be bigger. If the CM noise is 
> bigger than it introduces jitter into the differential signal. which is bad.
> 2.) Impedance:
> if the return path is poor, the the return current has to flow around to get 
> a path between the source and destination, so on some areas the return 
> current doesnt flow unterneath the signal traces so basically their 
> single-ended (odd mode) impedances (so the diff impedance too) will be 
> different than its calculated in the imp.calculator (polar, or MMTL), which 
> assumes a perfect ground plane.
>
> am i right, or wrong? why?
>
> Istvan Nagy
> Concurrent Technologies plc, UK.
>
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