[SI-LIST] current flow on a pwr plane

I've been looking at some simulators that predict DC current flow
through a power plane...They can be used to evaluate the ability of a
copper pour to support the DC current needs between a POL regulator and
it's "consumer" (maybe the core voltage of a processor or ASIC). This is
becoming important because of the "swiss cheese" effect under these
components and the huge DC currents that they need. 
Anyway, on to my question : the results of these simulations often show
current densities that are not intuitive to me. For example, 4 vias
connecting 2 pwr planes together, they are somewhat close to each other
(say, within an inch), yet the current densities through these 4 vias
are very different.

Is there a white paper or someone out there that can explain this
behavior? I'm not looking for a complex equation, more like an
explanation that makes it more intuitive.

Thank,
Jim Peterson
Honeywell

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