[SI-LIST] clock simulation

Guys,
Now I know that the clock net is a very critical net in the package and from
my package RLC extraction it is found that the inductance is pretty
significant on the clock net. Also it runs over all kinds of traces in the
package.

So how do I go about and simulate *relevant effects on clock signal by the
package*? This is something which hasn't been addressed before, so I m
basically setting up the simulation from scratch. What all issues will I
have to address? For example, do I need information about the clock
buffer/driver used and all that?

I would really appreciate if you guys can give me any insight on how I can
start.

Thanks a bunch,
Pras


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