[SI-LIST] Re: clock divider

When I'm counting dashes '-' below, it looks like (b) can be slightly 
delayed (9 - vs. 8 - for the original). If that's the case, then a 
rising edge triggered flip flop with feedback from its ~Q output will do 
the trick. Its reset value needs to be 0 (~Q will be 1).

If the edges of the original waveform and the (b) waveform have to be 
exactly synchronous without any delay, I think you'll need a PLL, which 
gives you 1/2 the frequency of its input, or you need to use the output 
of two flip flops, which are clocked by 2x the input clock.

However, I don't see why the propagation delay through the flip flop 
would break your application, i.e., why you couldn't compensate for that.

Happy Thanksgiving!

Stefan

Ahmet Tokuz wrote:

>Hello,
>I want to explain my problem in graphics. Hopefully it
>would be better to understand. 
>By the way, Dave thanks a lot for your proposal. 
>
>
>        /--------\        /---------\
>        |        |        |         |
>        |       |        |         |
>--------|        |--------|         |---------    
>
>
>(a)
>                  |------------------|
>                  |                  |
>------------------|                  |---------
>
>
>(b)
>
>         |------------------|
>         |                  |
>---------|                  |-----------------
>
>
>
>I am looking for a solution which guarantees that (b)
>is always the case.
>
>thanks
>
>
>-ahmet
>
>--- Ahmet Tokuz <atokuz@xxxxxxxxx> wrote:
>  
>
>>Hello,
>>
>>I was wondering whether there's a way of dividing
>>clock by 2 deterministicly. I mean there may be two
>>outputs.  However I am interested in the one with
>>where phase is synched. I mean both rising and
>>falling
>>edges are aligned. Are there any way to ensure that?
>>
>>thanks
>>
>>    
>>
>  
>

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